subsys_dp_a10_xcvr

2017.10.31.03:30:09 Datasheet
Overview

All Components
   a10_xcvr altera_xcvr_native_a10 17.1
Memory Map
  a10_xcvr
reconfig_avmm_ch0 

a10_xcvr

altera_xcvr_native_a10 v17.1


Parameters

message_level error
anlg_voltage 1_0V
anlg_link sr
protocol_mode basic_std
pma_mode basic
duplex_mode tx
channels 4
set_data_rate 5400
rcfg_iface_enable 0
enable_simple_interface 1
set_disconnect_analog_resets 0
bonded_mode pma_only
set_pcs_bonding_master Auto
pcs_bonding_master 0
tx_pma_clk_div 1
plls 1
pll_select 0
enable_port_tx_analog_reset_ack 1
enable_port_tx_pma_clkout 0
enable_port_tx_pma_div_clkout 0
tx_pma_div_clkout_divider 0
enable_port_tx_pma_iqtxrx_clkout 0
enable_port_tx_pma_elecidle 0
enable_port_tx_pma_qpipullup 0
enable_port_tx_pma_qpipulldn 0
enable_port_tx_pma_txdetectrx 0
enable_port_tx_pma_rxfound 0
enable_port_rx_seriallpbken_tx 0
enable_port_rx_seriallpbken 0
std_pcs_pma_width 20
display_std_tx_pld_pcs_width 40
std_low_latency_bypass_enable 0
std_tx_pcfifo_mode low_latency
enable_port_tx_std_pcfifo_full 0
enable_port_tx_std_pcfifo_empty 0
std_tx_byte_ser_mode Serialize x2
std_tx_8b10b_enable 0
std_tx_8b10b_disp_ctrl_enable 0
std_tx_bitslip_enable 0
enable_port_tx_std_bitslipboundarysel 0
std_tx_bitrev_enable 0
std_tx_byterev_enable 0
std_tx_polinv_enable 1
enable_port_tx_polinv 1
enable_ports_pipe_sw 0
enable_ports_pipe_hclk 0
enable_ports_pipe_g3_analog 0
generate_docs 1
rcfg_enable 1
rcfg_shared 1
rcfg_jtag_enable 0
rcfg_separate_avmm_busy 0
set_capability_reg_enable 1
set_user_identifier 0
set_csr_soft_logic_enable 1
set_prbs_soft_logic_enable 1
rcfg_file_prefix altera_xcvr_native_a10
rcfg_sv_file_enable 1
rcfg_h_file_enable 1
rcfg_mif_file_enable 1
rcfg_multi_enable 0
set_rcfg_emb_strm_enable 0
rcfg_reduced_files_enable 0
rcfg_profile_cnt 2
rcfg_profile_select 1
rcfg_profile_data0
rcfg_profile_data1
rcfg_profile_data2
rcfg_profile_data3
rcfg_profile_data4
rcfg_profile_data5
rcfg_profile_data6
rcfg_profile_data7
enable_analog_settings 0
anlg_tx_analog_mode user_custom
anlg_enable_tx_default_ovr 0
anlg_tx_vod_output_swing_ctrl 0
anlg_tx_pre_emp_sign_pre_tap_1t fir_pre_1t_neg
anlg_tx_pre_emp_switching_ctrl_pre_tap_1t 0
anlg_tx_pre_emp_sign_pre_tap_2t fir_pre_2t_neg
anlg_tx_pre_emp_switching_ctrl_pre_tap_2t 0
anlg_tx_pre_emp_sign_1st_post_tap fir_post_1t_neg
anlg_tx_pre_emp_switching_ctrl_1st_post_tap 0
anlg_tx_pre_emp_sign_2nd_post_tap fir_post_2t_neg
anlg_tx_pre_emp_switching_ctrl_2nd_post_tap 0
anlg_tx_slew_rate_ctrl slew_r7
anlg_tx_compensation_en enable
anlg_tx_term_sel r_r1
anlg_enable_rx_default_ovr 0
anlg_rx_one_stage_enable s1_mode
anlg_rx_eq_dc_gain_trim stg2_gain7
anlg_rx_adp_ctle_acgain_4s radp_ctle_acgain_4s_1
anlg_rx_adp_ctle_eqz_1s_sel radp_ctle_eqz_1s_sel_3
anlg_rx_adp_vga_sel radp_vga_sel_2
anlg_rx_adp_dfe_fxtap1 radp_dfe_fxtap1_0
anlg_rx_adp_dfe_fxtap2 radp_dfe_fxtap2_0
anlg_rx_adp_dfe_fxtap3 radp_dfe_fxtap3_0
anlg_rx_adp_dfe_fxtap4 radp_dfe_fxtap4_0
anlg_rx_adp_dfe_fxtap5 radp_dfe_fxtap5_0
anlg_rx_adp_dfe_fxtap6 radp_dfe_fxtap6_0
anlg_rx_adp_dfe_fxtap7 radp_dfe_fxtap7_0
anlg_rx_adp_dfe_fxtap8 radp_dfe_fxtap8_0
anlg_rx_adp_dfe_fxtap9 radp_dfe_fxtap9_0
anlg_rx_adp_dfe_fxtap10 radp_dfe_fxtap10_0
anlg_rx_adp_dfe_fxtap11 radp_dfe_fxtap11_0
anlg_rx_term_sel r_r1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)
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