subsys_dp_clk_16
2017.10.31.03:30:21
Datasheet
Overview
Memory Map
clk_16
altera_clock_bridge v17.1
Parameters
DERIVED_CLOCK_RATE
0
EXPLICIT_CLOCK_RATE
16000000
NUM_CLOCK_OUTPUTS
1
deviceFamily
UNKNOWN
generateLegacySim
false
Software Assignments
(none)
generation took 0.00 seconds
rendering took 0.00 seconds