subsys_dp_clk_vip

2017.11.02.03:24:15 Datasheet
Overview

Memory Map

clk_vip

altera_clock_bridge v17.1


Parameters

DERIVED_CLOCK_RATE 74250000
EXPLICIT_CLOCK_RATE 74250000
NUM_CLOCK_OUTPUTS 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)
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