subsys_dp_fpll_0

2017.11.02.03:24:43 Datasheet
Overview

All Components
   fpll_0 altera_xcvr_fpll_a10 17.1
Memory Map
  fpll_0
reconfig_avmm0 

fpll_0

altera_xcvr_fpll_a10 v17.1


Parameters

enable_pll_reconfig 1
rcfg_jtag_enable 0
rcfg_separate_avmm_busy 0
set_capability_reg_enable 0
set_user_identifier 0
set_csr_soft_logic_enable 0
rcfg_file_prefix altera_xcvr_fpll_a10
rcfg_sv_file_enable 1
rcfg_h_file_enable 0
rcfg_mif_file_enable 1
gui_fpll_mode 2
gui_hssi_prot_mode 0
gui_refclk_switch false
gui_refclk1_frequency 100.0
gui_switchover_mode Automatic Switchover
gui_switchover_delay 0
gui_enable_active_clk false
gui_enable_clk_bad false
generate_docs 1
gui_bw_sel medium
gui_is_downstream_cascaded_pll false
gui_desired_refclk_frequency 270.0
gui_actual_refclk_frequency 100.0
gui_operation_mode 0
gui_refclk_cnt 1
gui_refclk_index 0
gui_enable_fractional false
gui_enable_manual_hssi_counters false
enable_cascade_in 0
gui_hssi_output_clock_frequency 2700.0
gui_pll_datarate 5400.0
gui_number_of_output_clocks 1
gui_enable_phase_alignment false
gui_pfd_frequency 100.0
gui_desired_outclk0_frequency 100.0
gui_actual_outclk0_frequency 100.0
gui_outclk0_phase_shift_unit 0
gui_outclk0_desired_phase_shift 0.0
gui_outclk0_actual_phase_shift 0.0
gui_desired_hssi_cascade_frequency 100.0
enable_ext_lockdetect_ports 0
enable_mcgb 1
mcgb_div 1
enable_hfreq_clk 0
enable_mcgb_pcie_clksw 0
mcgb_aux_clkin_cnt 0
mcgb_in_clk_freq 2700.0
mcgb_out_datarate 5400.0
enable_bonding_clks 1
enable_fb_comp_bonding 0
pma_width 20
gui_parameter_list C-counter-0,C-counter-1,C-counter-2,C-counter-3,L-counter,M-counter,N-counter,VCO Frequency,pll_dsm_fractional_division
gui_parameter_values 1,1,1,1,2,20,1,10800.0 MHz,1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)
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