From 8e54a2a2cb2124636d9c881b5a28e93c8b29c53b Mon Sep 17 00:00:00 2001
From: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
Date: Fri, 27 Aug 2021 19:46:52 +0800
Subject: [PATCH] socfpga_stratix10_socdk: sgmii: include reference design dtsi

Signed-off-by: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
---
 .../dts/altera/socfpga_stratix10_sgmii.dtsi   | 89 +++++++++++++++++++
 .../dts/altera/socfpga_stratix10_socdk.dts    |  1 +
 2 files changed, 90 insertions(+)
 create mode 100644 arch/arm64/boot/dts/altera/socfpga_stratix10_sgmii.dtsi

diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_sgmii.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10_sgmii.dtsi
new file mode 100644
index 000000000000..6d5fdea8a9b4
--- /dev/null
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_sgmii.dtsi
@@ -0,0 +1,89 @@
+/*
+* Add this piece of dtsi fragment as #include "socfpga_stratix10_sgmii.dtsi"
+* in the file socfpga_stratix10_socdk.dts. Compile it in the kernel along with
+* socfpga_stratix10.dtsi.
+*/
+
+/{
+	soc {
+		clocks {
+			sgmii_1_clk_0: sgmii_1_clk_0 {
+                                compatible = "fixed-clock";
+                                #clock-cells = <0>;
+                                clock-frequency = <125000000>;  /* 125.00 MHz */
+                                clock-output-names = "sgmii_1_clk_0-out_clk";
+                        }; //end sgmii_1_clk_0 (sgmii_1_clk_0)
+
+                        sgmii_1_clk_125: sgmii_1_clk_125 {
+                                compatible = "fixed-clock";
+                                #clock-cells = <0>;
+                                clock-frequency = <125000000>;  /* 125.00 MHz */
+                                clock-output-names = "sgmii_1_clk_125-out_clk";
+                        }; //end sgmii_1_clk_125 (sgmii_1_clk_125)
+
+                        sgmii_2_clk_0: sgmii_2_clk_0 {
+                                compatible = "fixed-clock";
+                                #clock-cells = <0>;
+                                clock-frequency = <125000000>;  /* 125.00 MHz */
+                                clock-output-names = "sgmii_2_clk_0-out_clk";
+                        }; //end sgmii_2_clk_0 (sgmii_2_clk_0)
+
+                        sgmii_2_clk_125: sgmii_2_clk_125 {
+                                compatible = "fixed-clock";
+                                #clock-cells = <0>;
+                                clock-frequency = <125000000>;  /* 125.00 MHz */
+                                clock-output-names = "sgmii_2_clk_125-out_clk";
+                        }; //end sgmii_2_clk_125 (sgmii_2_clk_125)
+		};
+
+		s10_hps_bridges: bridge@80000000 {
+                        compatible = "altr,bridge-18.1", "simple-bus";
+                        reg = <0x80000000 0x60000000>,
+                                <0xf9000000 0x00100000>;
+                        reg-names = "axi_h2f", "axi_h2f_lw";
+                        //clocks = <&iopll_0 1 &clk_0 &dp_0_video_pll 3 &iopll_0 0>;
+                        //clock-names = "h2f_axi_clock", "h2f_lw_axi_clock", "f2sdram0_clock", "f2sdram2_clock";
+                        #address-cells = <2>;
+                        #size-cells = <1>;
+                        ranges = <0x00000000 0x00000000 0x80000000 0x00040000>,
+                                <0x00000001 0x00000000 0xf9010000 0x00000040>,
+                                <0x00000001 0x00000040 0xf9010040 0x00000008>,
+                                <0x00000001 0x0000080 0xf9010080 0x00000040>,
+                                <0x00000001 0x00000c0 0xf90100c0 0x00000008>;
+
+                        sgmii_1_gmii2sgmii: phy@0x100000040 {
+                                compatible = "altr,gmii-to-sgmii-2.0";
+                                reg = <0x00000001 0x00000000 0x00000040>,
+                                        <0x00000001 0x00000040 0x00000008>;
+                                reg-names = "eth_tse_control_port", "gmii_to_sgmii_adapter_avalon_slave";
+                                clocks = <&sgmii_1_clk_0 &gmac1 1 &sgmii_1_clk_125 &sgmii_1_clk_125>;
+                                clock-names = "clock_in", "emac_gtx_clk", "tse_pcs_ref_clk_clock_connection", "tse_rx_cdr_refclk";
+                        }; //end phy@0x100000040 (sgmii_1_gmii2sgmii)
+
+                        sgmii_2_gmii2sgmii: phy@0x100000c0 {
+                                compatible = "altr,gmii-to-sgmii-2.0";
+                                reg = <0x00000001 0x00000080 0x00000040>,
+                                        <0x00000001 0x000000c0 0x00000008>;
+                                reg-names = "eth_tse_control_port", "gmii_to_sgmii_adapter_avalon_slave";
+                                clocks = <&sgmii_2_clk_0 &gmac2 1 &sgmii_2_clk_125 &sgmii_2_clk_125>;
+                                clock-names = "clock_in", "emac_gtx_clk", "tse_pcs_ref_clk_clock_connection", "tse_rx_cdr_refclk";
+                        }; //end phy@0x1000000c0 (sgmii_2_gmii2sgmii)
+                };
+
+	};
+};
+
+&gmac1 {
+        altr,gmii-to-sgmii-converter = <&sgmii_1_gmii2sgmii>;
+        altr,gmii_to_sgmii_converter = <&sgmii_1_gmii2sgmii>;
+        phy-mode = "sgmii";
+        status = "okay";
+};
+
+&gmac2 {
+        altr,gmii-to-sgmii-converter = <&sgmii_2_gmii2sgmii>;
+        altr,gmii_to_sgmii_converter = <&sgmii_2_gmii2sgmii>;
+        phy-mode = "sgmii";
+        status = "okay";
+};
+
diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
index 5203cb0eeedc..60fbf33b0234 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
@@ -5,6 +5,7 @@
 
 #include "socfpga_stratix10.dtsi"
 #include "socfpga_stratix10_qse.dtsi"
+#include "socfpga_stratix10_sgmii.dtsi"
 
 / {
 	model = "SoCFPGA Stratix 10 SoCDK";
-- 
2.17.1

