// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2025 Altera Corporation
 *
 */

/dts-v1/;

/ {
	description = "FIT image with kernel, DTB and FPGA core binary";
	#address-cells = <1>;

	images {
		kernel {
			description = "Linux Kernel";
			data = /incbin/("./Image.lzma");
			type = "kernel";
			arch = "arm64";
			os = "linux";
			compression = "lzma";
			load = <0x6000000>;
			entry = <0x6000000>;
			hash {
				algo = "crc32";
			};
		};

		fdt-0 {
			description = "socfpga_socdk_vanilla";
			data = /incbin/("./socfpga_stratix10_vanilla.dtb");
			type = "flat_dt";
			arch = "arm64";
			compression = "none";
			hash {
				algo = "crc32";
			};
		};

		fdt-1 {
			description = "socfpga_socdk_nand";
			data = /incbin/("./socfpga_stratix10_socdk_nand.dtb");
			type = "flat_dt";
			arch = "arm64";
			compression = "none";
			hash {
				algo = "crc32";
			};
		};

		fdt-2 {
			description = "socfpga_socdk_emmc";
			data = /incbin/("./socfpga_stratix10_socdk_emmc.dtb");
			type = "flat_dt";
			arch = "arm64";
			compression = "none";
			hash {
				algo = "crc32";
			};
		};

		fdt-3 {
			description = "socfpga_socdk_pr";
			data = /incbin/("./socfpga_stratix10_socdk_pr.dtb");
			type = "flat_dt";
			arch = "arm64";
			compression = "none";
			hash {
				algo = "crc32";
			};
		};

		fdt-4 {
			description = "socfpga_socdk_combined";
			data = /incbin/("./socfpga_stratix10_socdk.dtb");
			type = "flat_dt";
			arch = "arm64";
			compression = "none";
			hash {
				algo = "crc32";
			};
		};

		fpga-1 {
			description = "FPGA bitstream for NAND";
			data = /incbin/("./nand.core.rbf");
			type = "fpga";
			arch = "arm64";
			compression = "none";
			load = <0xA000000>;
			hash {
				algo = "crc32";
			};
		};

		fpga-2 {
			description = "FPGA bitstream for EMMC";
			data = /incbin/("./emmc.core.rbf");
			type = "fpga";
			arch = "arm64";
			compression = "none";
			load = <0xA000000>;
			hash {
				algo = "crc32";
			};
		};

		fpga-3 {
			description = "FPGA bitstream for PR";
			data = /incbin/("./ghrd_pr.core.rbf");
			type = "fpga";
			arch = "arm64";
			compression = "none";
			load = <0xA000000>;
			hash {
				algo = "crc32";
			};
		};

		fpga-4 {
			description = "FPGA bitstream for GHRD";
			data = /incbin/("./ghrd.core.rbf");
			type = "fpga";
			arch = "arm64";
			compression = "none";
			load = <0xA000000>;
			hash {
				algo = "crc32";
			};
		};
	};

	configurations {
		default = "board-0";

		board-0 {
			description = "board_0";
			kernel = "kernel";
			fdt = "fdt-0";
			signature {
				algo = "crc32";
				key-name-hint = "dev";
				sign-images = "fdt-0", "kernel";
			};
		};

		board-1 {
			description = "board_1";
			kernel = "kernel";
			fdt = "fdt-1";
			fpga = "fpga-1";
			signature {
				algo = "crc32";
				key-name-hint = "dev";
				sign-images = "fdt-1", "kernel", "fpga-1";
			};
		};

		board-2 {
			description = "board_2";
			kernel = "kernel";
			fdt = "fdt-2";
			fpga = "fpga-2";
			signature {
				algo = "crc32";
				key-name-hint = "dev";
				sign-images = "fdt-2", "kernel", "fpga-2";
			};
		};

		board-3 {
			description = "board_3";
			kernel = "kernel";
			fdt = "fdt-3";
			fpga = "fpga-3";
			signature {
				algo = "crc32";
				key-name-hint = "dev";
				sign-images = "fdt-3", "kernel", "fpga-3";
			};
		};

		board-4 {
			description = "board_4";
			kernel = "kernel";
			fdt = "fdt-4";
			fpga = "fpga-4";
			signature {
				algo = "crc32";
				key-name-hint = "dev";
				sign-images = "fdt-4", "kernel", "fpga-4";
			};
		};
	};
};