# PIN MAP for core < hps_sdram_p0 >
#
# Generated by hps_sdram_p0_pin_assignments.tcl
#
# This file is for reference only and is not used by Quartus Prime
#

INSTANCE: soc_inst|hps_0|hps_io|border|hps_sdram_inst
DQS: {hps_memory_mem_dqs[0]} {hps_memory_mem_dqs[1]} {hps_memory_mem_dqs[2]} {hps_memory_mem_dqs[3]} {hps_memory_mem_dqs[4]}
DQSn: {hps_memory_mem_dqs_n[0]} {hps_memory_mem_dqs_n[1]} {hps_memory_mem_dqs_n[2]} {hps_memory_mem_dqs_n[3]} {hps_memory_mem_dqs_n[4]}
DQ: {{hps_memory_mem_dq[0]} {hps_memory_mem_dq[1]} {hps_memory_mem_dq[2]} {hps_memory_mem_dq[3]} {hps_memory_mem_dq[4]} {hps_memory_mem_dq[5]} {hps_memory_mem_dq[6]} {hps_memory_mem_dq[7]}} {{hps_memory_mem_dq[8]} {hps_memory_mem_dq[9]} {hps_memory_mem_dq[10]} {hps_memory_mem_dq[11]} {hps_memory_mem_dq[12]} {hps_memory_mem_dq[13]} {hps_memory_mem_dq[14]} {hps_memory_mem_dq[15]}} {{hps_memory_mem_dq[16]} {hps_memory_mem_dq[17]} {hps_memory_mem_dq[18]} {hps_memory_mem_dq[19]} {hps_memory_mem_dq[20]} {hps_memory_mem_dq[21]} {hps_memory_mem_dq[22]} {hps_memory_mem_dq[23]}} {{hps_memory_mem_dq[24]} {hps_memory_mem_dq[25]} {hps_memory_mem_dq[26]} {hps_memory_mem_dq[27]} {hps_memory_mem_dq[28]} {hps_memory_mem_dq[29]} {hps_memory_mem_dq[30]} {hps_memory_mem_dq[31]}} {{hps_memory_mem_dq[32]} {hps_memory_mem_dq[33]} {hps_memory_mem_dq[34]} {hps_memory_mem_dq[35]} {hps_memory_mem_dq[36]} {hps_memory_mem_dq[37]} {hps_memory_mem_dq[38]} {hps_memory_mem_dq[39]}}
DM {hps_memory_mem_dm[0]} {hps_memory_mem_dm[1]} {hps_memory_mem_dm[2]} {hps_memory_mem_dm[3]} {hps_memory_mem_dm[4]}
CK: hps_memory_mem_ck
CKn: hps_memory_mem_ck_n
ADD: {hps_memory_mem_a[0]} {hps_memory_mem_a[10]} {hps_memory_mem_a[11]} {hps_memory_mem_a[12]} {hps_memory_mem_a[13]} {hps_memory_mem_a[14]} {hps_memory_mem_a[1]} {hps_memory_mem_a[2]} {hps_memory_mem_a[3]} {hps_memory_mem_a[4]} {hps_memory_mem_a[5]} {hps_memory_mem_a[6]} {hps_memory_mem_a[7]} {hps_memory_mem_a[8]} {hps_memory_mem_a[9]}
CMD: hps_memory_mem_cas_n hps_memory_mem_cke hps_memory_mem_cs_n hps_memory_mem_odt hps_memory_mem_ras_n hps_memory_mem_we_n
RESET: hps_memory_mem_reset_n
BA: {hps_memory_mem_ba[0]} {hps_memory_mem_ba[1]} {hps_memory_mem_ba[2]}
PLL CK: soc_system:soc_inst|soc_system_hps_0:hps_0|soc_system_hps_0_hps_io:hps_io|soc_system_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|afi_clk
PLL DQ WRITE: soc_system:soc_inst|soc_system_hps_0:hps_0|soc_system_hps_0_hps_io:hps_io|soc_system_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk
PLL WRITE: soc_system:soc_inst|soc_system_hps_0:hps_0|soc_system_hps_0_hps_io:hps_io|soc_system_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|afi_clk
PLL DRIVER CORE: _UNDEFINED_PIN_
DQS_IN_CLOCK DQS_PIN (0): hps_memory_mem_dqs[0]
DQS_IN_CLOCK DQS_SHIFTED_PIN (0): soc_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|dqs_delay_chain|dqsbusout
DQS_IN_CLOCK DIV_NAME (0): soc_inst|hps_0|hps_io|border|hps_sdram_inst|div_clock_0
DQS_IN_CLOCK DIV_PIN (0): soc_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[0]
DQS_IN_CLOCK DQS_PIN (1): hps_memory_mem_dqs[1]
DQS_IN_CLOCK DQS_SHIFTED_PIN (1): soc_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|dqs_delay_chain|dqsbusout
DQS_IN_CLOCK DIV_NAME (1): soc_inst|hps_0|hps_io|border|hps_sdram_inst|div_clock_1
DQS_IN_CLOCK DIV_PIN (1): soc_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[1]
DQS_IN_CLOCK DQS_PIN (2): hps_memory_mem_dqs[2]
DQS_IN_CLOCK DQS_SHIFTED_PIN (2): soc_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|dqs_delay_chain|dqsbusout
DQS_IN_CLOCK DIV_NAME (2): soc_inst|hps_0|hps_io|border|hps_sdram_inst|div_clock_2
DQS_IN_CLOCK DIV_PIN (2): soc_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[2]
DQS_IN_CLOCK DQS_PIN (3): hps_memory_mem_dqs[3]
DQS_IN_CLOCK DQS_SHIFTED_PIN (3): soc_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|dqs_delay_chain|dqsbusout
DQS_IN_CLOCK DIV_NAME (3): soc_inst|hps_0|hps_io|border|hps_sdram_inst|div_clock_3
DQS_IN_CLOCK DIV_PIN (3): soc_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[3]
DQS_IN_CLOCK DQS_PIN (4): hps_memory_mem_dqs[4]
DQS_IN_CLOCK DQS_SHIFTED_PIN (4): soc_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_inst|dqs_delay_chain|dqsbusout
DQS_IN_CLOCK DIV_NAME (4): soc_inst|hps_0|hps_io|border|hps_sdram_inst|div_clock_4
DQS_IN_CLOCK DIV_PIN (4): soc_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|read_capture_clk_div2[4]
DQS_OUT_CLOCK SRC (0): soc_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|obuf_os_0|o
DQS_OUT_CLOCK DST (0): hps_memory_mem_dqs[0]
DQS_OUT_CLOCK DM (0): hps_memory_mem_dm[0]
DQS_OUT_CLOCK SRC (1): soc_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|obuf_os_0|o
DQS_OUT_CLOCK DST (1): hps_memory_mem_dqs[1]
DQS_OUT_CLOCK DM (1): hps_memory_mem_dm[1]
DQS_OUT_CLOCK SRC (2): soc_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|obuf_os_0|o
DQS_OUT_CLOCK DST (2): hps_memory_mem_dqs[2]
DQS_OUT_CLOCK DM (2): hps_memory_mem_dm[2]
DQS_OUT_CLOCK SRC (3): soc_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|obuf_os_0|o
DQS_OUT_CLOCK DST (3): hps_memory_mem_dqs[3]
DQS_OUT_CLOCK DM (3): hps_memory_mem_dm[3]
DQS_OUT_CLOCK SRC (4): soc_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_inst|obuf_os_0|o
DQS_OUT_CLOCK DST (4): hps_memory_mem_dqs[4]
DQS_OUT_CLOCK DM (4): hps_memory_mem_dm[4]
DQSN_OUT_CLOCK SRC (0): soc_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|obuf_os_bar_0|o
DQSN_OUT_CLOCK DST (0): hps_memory_mem_dqs_n[0]
DQSN_OUT_CLOCK DM (0): hps_memory_mem_dm[0]
DQSN_OUT_CLOCK SRC (1): soc_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|obuf_os_bar_0|o
DQSN_OUT_CLOCK DST (1): hps_memory_mem_dqs_n[1]
DQSN_OUT_CLOCK DM (1): hps_memory_mem_dm[1]
DQSN_OUT_CLOCK SRC (2): soc_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|obuf_os_bar_0|o
DQSN_OUT_CLOCK DST (2): hps_memory_mem_dqs_n[2]
DQSN_OUT_CLOCK DM (2): hps_memory_mem_dm[2]
DQSN_OUT_CLOCK SRC (3): soc_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|obuf_os_bar_0|o
DQSN_OUT_CLOCK DST (3): hps_memory_mem_dqs_n[3]
DQSN_OUT_CLOCK DM (3): hps_memory_mem_dm[3]
DQSN_OUT_CLOCK SRC (4): soc_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_inst|obuf_os_bar_0|o
DQSN_OUT_CLOCK DST (4): hps_memory_mem_dqs_n[4]
DQSN_OUT_CLOCK DM (4): hps_memory_mem_dm[4]
READ CAPTURE DDIO: {*:soc_inst|*:hps_0|*:hps_io|*:border|*:hps_sdram_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg~DFFLO} {*:soc_inst|*:hps_0|*:hps_io|*:border|*:hps_sdram_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].aligned_input[*]}
AFI RESET REGISTERS: *:soc_inst|*:hps_0|*:hps_io|*:border|*:hps_sdram_inst|*:p0|*:umemphy|*:ureset|*:ureset_afi_clk|reset_reg[3]
SYNCHRONIZERS: *:soc_inst|*:hps_0|*:hps_io|*:border|*:hps_sdram_inst|*:p0|*:umemphy|*:uread_datapath|read_buffering[*].seq_read_fifo_reset_sync
SYNCHRONIZATION FIFO WRITE ADDRESS REGISTERS: *:soc_inst|*:hps_0|*:hps_io|*:border|*:hps_sdram_inst|*:p0|*:umemphy|*:uread_datapath|read_buffering[*].read_subgroup[*].wraddress[*]
SYNCHRONIZATION FIFO WRITE REGISTERS: *:soc_inst|*:hps_0|*:hps_io|*:border|*:hps_sdram_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|input_path_gen[*].read_fifo|*INPUT_DFF*
SYNCHRONIZATION FIFO READ REGISTERS: *:soc_inst|*:hps_0|*:hps_io|*:border|*:hps_sdram_inst|*:p0|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|input_path_gen[*].read_fifo|dout[*]

#
# END OF INSTANCE: soc_inst|hps_0|hps_io|border|hps_sdram_inst

