fpga_rgmii_subsys

2025.01.17.16:49:29 Datasheet
Overview

Memory Map

clock_in

altera_clock_bridge v19.2.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

intel_gmii_to_rgmii_converter_0

intel_gmii_to_rgmii_converter v1.2.0
clock_in out_clk   intel_gmii_to_rgmii_converter_0
  peri_clock
iopll_0 outclk0  
  pll_25m_clock
outclk1  
  pll_2_5m_clock
locked  
  locked_pll_tx
reset_in out_reset  
  peri_reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

iopll_0

altera_iopll v20.0.0
clock_in out_clk   iopll_0
  refclk
reset_in out_reset  
  reset
outclk0   intel_gmii_to_rgmii_converter_0
  pll_25m_clock
outclk1  
  pll_2_5m_clock
locked  
  locked_pll_tx


Parameters

generateLegacySim false
  

Software Assignments

(none)

reset_in

altera_reset_bridge v19.2.0
clock_in out_clk   reset_in
  clk
out_reset   intel_gmii_to_rgmii_converter_0
  peri_reset
out_reset   iopll_0
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)
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