jtag_subsys

2025.01.17.16:49:41 Datasheet
Overview

Memory Map
fpga_m hps_f2sdram hps_m
 master  master  master

fpga_m

altera_jtag_avalon_master v19.1
jtag_clk out_clk   fpga_m
  clk
jtag_rst_in out_reset  
  clk_reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

hps_f2sdram

altera_jtag_avalon_master v19.1
jtag_clk out_clk   hps_f2sdram
  clk
jtag_rst_in out_reset  
  clk_reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

hps_m

altera_jtag_avalon_master v19.1
jtag_clk out_clk   hps_m
  clk
jtag_rst_in out_reset  
  clk_reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

jtag_clk

altera_clock_bridge v19.2.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

jtag_rst_in

altera_reset_bridge v19.2.0


Parameters

generateLegacySim false
  

Software Assignments

(none)
generation took 0.00 seconds rendering took 0.00 seconds