emif_io96b_hps_emif_io96b_hps_200_g4nkt2a_emif_0_ddr4comp

2025.01.17.17:37:20 Datasheet
Overview

Memory Map
emif_0_ddr4comp_cal_0 emif_0_ddr4comp_cal_0_cal_0 emif_0_ddr4comp_cal_0_cal_0_jamb emif_0_ddr4comp_cal_0_cal_0_jamb_jamb
 m0_axi4lite  m0_axi4lite  master  master
  emif_0_ddr4comp_cal_0
s0_axi4lite 
s0_noc_axi4lite 
s0_noc_axi4litenoc 
  emif_0_ddr4comp_cal_0_cal_0
s0_axi4lite 
s0_noc_axi4lite 
s0_noc_axi4litenoc 

emif_0_ddr4comp

emif_io96b_ddr4comp v2.0.0


Parameters

MEM_CHANNEL_DATA_DQ_WIDTH 32
MEM_CHANNEL_ECC_DQ_WIDTH 0
MEM_DIE_DQ_WIDTH 8
MEM_DIE_DENSITY_GBITS 16
MEM_CHANNEL_CS_WIDTH 1
MEM_SPEEDBIN 1600L
MEM_AC_PARITY_EN false
MEM_OPERATING_FREQ_MHZ_AUTOSET_EN false
MEM_OPERATING_FREQ_MHZ 800
CTRL_DM_EN false
CTRL_WR_DBI_EN false
CTRL_RD_DBI_EN false
TURNAROUND_R2W_SAMECS_CYC 0
TURNAROUND_R2R_SAMECS_CYC 0
TURNAROUND_W2W_SAMECS_CYC 0
TURNAROUND_W2R_SAMECS_CYC 0
PHY_REFCLK_FREQ_MHZ_AUTOSET_EN false
PHY_REFCLK_ADVANCED_SELECT_EN false
PHY_REFCLK_FREQ_MHZ 100.0
PHY_AC_PLACEMENT BOT
PHY_ALERT_N_PLACEMENT AC2
PHY_FORCE_MIN_4_AC_LANES_EN false
PHY_MAINBAND_ACCESS_MODE HARD_PATH
PHY_SIDEBAND_ACCESS_MODE HARD_PATH
PHY_SWIZZLE_MAP BYTE_SWIZZLE_CH0=3 X X X 0 2 1 X;PIN_SWIZZLE_CH0_DQS0=7 1 2 3 4 5 6 0;PIN_SWIZZLE_CH0_DQS1=15 14 13 12 11 10 9 8;PIN_SWIZZLE_CH0_DQS2=20 21 22 23 16 17 18 19;PIN_SWIZZLE_CH0_DQS3=31 24 25 26 27 28 29 30;
DEBUG_TOOLS_EN false
INSTANCE_ID 0
ADV_CAL_ENABLE_MARGIN false
ADV_CAL_ENABLE_REQ true
ADV_CAL_ENABLE_WEQ true
MEM_WR_PREAMBLE_MODE 1.0
MEM_RD_PREAMBLE_MODE 1.0
MEM_CL_CYC 12.0
MEM_CWL_CYC 9.0
MEM_TREFI_NS 7800.0
MEM_TRAS_NS 35.0
MEM_TRCD_NS 15.0
MEM_TRP_NS 15.0
MEM_TRC_NS 50.0
MEM_TCCD_L_NS 5.0
MEM_TCCD_S_NS 4.0
MEM_TRRD_L_NS 6.0
MEM_TRRD_S_NS 5.0
MEM_TFAW_NS 35.0
MEM_TWTR_L_NS 6.0
MEM_TWTR_S_NS 2.0
MEM_TWR_NS 15.0
MEM_TMRD_NS 8.0
MEM_TCKSRE_NS 8.0
MEM_TCKSRX_NS 8.0
MEM_TCKE_NS 4.0
MEM_TCKESR_CYC 5.0
MEM_TMPRR_NS 1.0
MEM_TRFC_NS 550.0
MEM_TDQSCK_NS 0.0
MEM_TDQSS_CYC 0.0
MEM_TDSH_NS 0.18
MEM_TDSS_NS 0.18
MEM_TIH_NS 140000.0
MEM_TIS_NS 115000.0
MEM_TQSH_NS 0.4
MEM_TWLH_NS 0.13
MEM_TWLS_NS 0.13
MEM_TRFC_DLR_NS 190.0
MEM_TRRD_DLR_NS 4.0
MEM_TFAW_DLR_NS 20.0
MEM_TCCD_DLR_NS 5.0
MEM_TXP_NS 5.0
MEM_TXS_NS 560.0
MEM_TXS_DLL_NS 597.0
MEM_TCPDED_NS 4.0
MEM_TMOD_NS 24.0
MEM_TZQCS_NS 128.0
MEM_TZQINIT_CYC 1024.0
MEM_TZQOPER_CYC 512.0
JEDEC_OVERRIDE_TABLE_PARAM_NAME MEM_TRAS_NS,MEM_TCCD_L_NS,MEM_TCCD_S_NS,MEM_TRRD_L_NS,MEM_TFAW_NS,MEM_TWTR_L_NS,MEM_TWTR_S_NS,MEM_TMRD_NS,MEM_TCKSRE_NS,MEM_TCKSRX_NS,MEM_TCKE_NS,MEM_TMPRR_NS,MEM_TDSH_NS,MEM_TDSS_NS,MEM_TIH_NS,MEM_TIS_NS,MEM_TQSH_NS,MEM_TWLH_NS,MEM_TWLS_NS,MEM_TRFC_DLR_NS,MEM_TRRD_DLR_NS,MEM_TFAW_DLR_NS,MEM_TCCD_DLR_NS,MEM_TXP_NS,MEM_TXS_DLL_NS,MEM_TCPDED_NS,MEM_TMOD_NS,MEM_TZQCS_NS
EX_DESIGN_HDL_FORMAT VERILOG
EX_DESIGN_GEN_SYNTH true
EX_DESIGN_GEN_SIM true
EX_DESIGN_USER_PLL_OUTPUT_FREQ_MHZ_AUTOSET_EN true
EX_DESIGN_USER_PLL_OUTPUT_FREQ_MHZ 200.0
EX_DESIGN_USER_PLL_REFCLK_FREQ_MHZ 100.0
EX_DESIGN_NOC_PLL_REFCLK_FREQ_MHZ 100
EX_DESIGN_TG_CSR_ACCESS_MODE JTAG
EX_DESIGN_TG_PROGRAM MEDIUM
EX_DESIGN_PMON_CH0_EN false
PHY_TERM_X_R_S_AC_OUTPUT_OHM SERIES_34_OHM_CAL
PHY_TERM_X_R_S_CK_OUTPUT_OHM SERIES_34_OHM_CAL
PHY_TERM_X_R_S_DQ_OUTPUT_OHM SERIES_34_OHM_CAL
PHY_TERM_X_DQ_SLEW_RATE FASTEST
PHY_TERM_X_R_T_DQ_INPUT_OHM RT_50_OHM_CAL
PHY_TERM_X_DQ_VREF 68.3
PHY_TERM_X_R_T_REFCLK_INPUT_OHM RT_DIFF
MEM_ODT_DQ_X_TGT_WR 4
MEM_ODT_DQ_X_NON_TGT_WR off
MEM_ODT_DQ_X_NON_TGT_RD off
MEM_ODT_DQ_X_RON 7
MEM_VREF_DQ_X_RANGE 2
MEM_VREF_DQ_X_VALUE 67.75
ANALOG_PARAM_DERIVATION_PARAM_NAME
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

emif_0_ddr4comp_cal_0

emif_io96b_ddr4comp_emif_io96b_cal v2.0.0


Parameters

INSTANCE_ID 0
NUM_CALBUS_PERIPHS 1
NUM_CALBUS_PLLS 0
PORT_S_AXIL_MODE HARD_PATH
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

emif_0_ddr4comp_cal_0_cal_0

emif_io96b_cal v2.0.0


Parameters

INSTANCE_ID 0
NUM_CALBUS_PERIPHS 1
NUM_CALBUS_PLLS 0
PORT_S_AXIL_MODE HARD_PATH
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

emif_0_ddr4comp_cal_0_cal_0_jamb

emif_io96b_cal_alt_mem_if_jtag_master v2.0.0


Parameters

USE_PLI 0
PLI_PORT 50000
FAST_VER 0
FIFO_DEPTHS 2
generateLegacySim false
  

Software Assignments

(none)

emif_0_ddr4comp_cal_0_cal_0_jamb_jamb

alt_mem_if_jtag_master v19.1


Parameters

USE_PLI 0
PLI_PORT 50000
FAST_VER 0
FIFO_DEPTHS 2
generateLegacySim false
  

Software Assignments

(none)
generation took 0.01 seconds rendering took 0.13 seconds