emif_io96b_hps_emif_io96b_hps_100_p3irrua_refclk_bridge
2024.11.19.22:33:20
Datasheet
Overview
Memory Map
refclk_bridge
qsys_interface_bridge v1.0
Parameters
INTERFACES
refclk_in clock sink,refclk_out clock source,refclk_in_gpio conduit end,refclk_out_gpio conduit start
PORTS
refclk_in refclk_in clk input 1,refclk_out refclk_out clk output 1,refclk_in_gpio refclk_in_gpio export output 1,refclk_out_gpio refclk_out_gpio export input 1
CONNECTIONS
refclk_in refclk_in_gpio,refclk_out_gpio refclk_out
CUSTOM_ELABORATION_COMMANDS
deviceFamily
UNKNOWN
generateLegacySim
false
Software Assignments
(none)
generation took 0.00 seconds
rendering took 0.09 seconds