MEM_CHANNEL_DATA_DQ_WIDTH |
32 |
MEM_CHANNEL_ECC_DQ_WIDTH |
0 |
MEM_DIE_DQ_WIDTH |
8 |
MEM_DIE_DENSITY_GBITS |
16 |
MEM_CHANNEL_CS_WIDTH |
1 |
MEM_SPEEDBIN |
1600L |
MEM_AC_PARITY_EN |
false |
MEM_OPERATING_FREQ_MHZ_AUTOSET_EN |
false |
MEM_OPERATING_FREQ_MHZ |
800 |
CTRL_DM_EN |
false |
CTRL_WR_DBI_EN |
false |
CTRL_RD_DBI_EN |
false |
TURNAROUND_R2W_SAMECS_CYC |
0 |
TURNAROUND_W2R_SAMECS_CYC |
0 |
PHY_REFCLK_FREQ_MHZ_AUTOSET_EN |
false |
PHY_REFCLK_ADVANCED_SELECT_EN |
false |
PHY_REFCLK_FREQ_MHZ |
150.0 |
PHY_AC_PLACEMENT |
BOT |
PHY_ALERT_N_PLACEMENT |
AC2 |
PHY_FORCE_MIN_4_AC_LANES_EN |
false |
PHY_MAINBAND_ACCESS_MODE |
HARD_PATH |
PHY_SIDEBAND_ACCESS_MODE |
HARD_PATH |
PHY_SWIZZLE_MAP |
BYTE_SWIZZLE_CH0=0 X X X 1 2 3 X;PIN_SWIZZLE_CH0_DQS3=26 30 28 24 25 27 29 31;PIN_SWIZZLE_CH0_DQS2=16 20 22 18 23 21 19 17;PIN_SWIZZLE_CH0_DQS1=14 11 12 8 10 9 13 15;PIN_SWIZZLE_CH0_DQS0=2 0 6 4 7 5 3 1; |
DEBUG_TOOLS_EN |
false |
INSTANCE_ID |
0 |
MEM_WR_PREAMBLE_MODE |
1.0 |
MEM_RD_PREAMBLE_MODE |
1.0 |
MEM_CL_CYC |
12.0 |
MEM_CWL_CYC |
9.0 |
MEM_TREFI_NS |
7800.0 |
MEM_TRAS_NS |
35.0 |
MEM_TRCD_NS |
15.0 |
MEM_TRP_NS |
15.0 |
MEM_TRC_NS |
50.0 |
MEM_TCCD_L_NS |
5.0 |
MEM_TCCD_S_NS |
4.0 |
MEM_TRRD_L_NS |
6.0 |
MEM_TRRD_S_NS |
5.0 |
MEM_TFAW_NS |
35.0 |
MEM_TWTR_L_NS |
6.0 |
MEM_TWTR_S_NS |
2.0 |
MEM_TWR_NS |
15.0 |
MEM_TMRD_NS |
8.0 |
MEM_TCKSRE_NS |
8.0 |
MEM_TCKSRX_NS |
8.0 |
MEM_TCKE_NS |
4.0 |
MEM_TCKESR_CYC |
5.0 |
MEM_TMPRR_NS |
1.0 |
MEM_TRFC_NS |
550.0 |
MEM_TDQSCK_NS |
0.0 |
MEM_TDQSS_CYC |
0.0 |
MEM_TDSH_NS |
0.18 |
MEM_TDSS_NS |
0.18 |
MEM_TIH_NS |
140000.0 |
MEM_TIS_NS |
115000.0 |
MEM_TQSH_NS |
0.4 |
MEM_TWLH_NS |
0.13 |
MEM_TWLS_NS |
0.13 |
MEM_TRFC_DLR_NS |
190.0 |
MEM_TRRD_DLR_NS |
4.0 |
MEM_TFAW_DLR_NS |
20.0 |
MEM_TCCD_DLR_NS |
5.0 |
MEM_TXP_NS |
5.0 |
MEM_TXS_NS |
560.0 |
MEM_TXS_DLL_NS |
597.0 |
MEM_TCPDED_NS |
4.0 |
MEM_TMOD_NS |
24.0 |
MEM_TZQCS_NS |
128.0 |
MEM_TZQINIT_CYC |
1024.0 |
MEM_TZQOPER_CYC |
512.0 |
JEDEC_OVERRIDE_TABLE_PARAM_NAME |
MEM_TRAS_NS,MEM_TCCD_L_NS,MEM_TCCD_S_NS,MEM_TRRD_L_NS,MEM_TFAW_NS,MEM_TWTR_L_NS,MEM_TWTR_S_NS,MEM_TMRD_NS,MEM_TCKSRE_NS,MEM_TCKSRX_NS,MEM_TCKE_NS,MEM_TMPRR_NS,MEM_TDSH_NS,MEM_TDSS_NS,MEM_TIH_NS,MEM_TIS_NS,MEM_TQSH_NS,MEM_TWLH_NS,MEM_TWLS_NS,MEM_TRFC_DLR_NS,MEM_TRRD_DLR_NS,MEM_TFAW_DLR_NS,MEM_TCCD_DLR_NS,MEM_TXP_NS,MEM_TXS_DLL_NS,MEM_TCPDED_NS,MEM_TMOD_NS,MEM_TZQCS_NS |
EX_DESIGN_HDL_FORMAT |
VERILOG |
EX_DESIGN_GEN_SYNTH |
true |
EX_DESIGN_GEN_SIM |
true |
EX_DESIGN_USER_PLL_OUTPUT_FREQ_MHZ_AUTOSET_EN |
true |
EX_DESIGN_USER_PLL_OUTPUT_FREQ_MHZ |
200.0 |
EX_DESIGN_USER_PLL_REFCLK_FREQ_MHZ |
100.0 |
EX_DESIGN_NOC_PLL_REFCLK_FREQ_MHZ |
100 |
EX_DESIGN_TG_CSR_ACCESS_MODE |
JTAG |
EX_DESIGN_TG_PROGRAM |
MEDIUM |
EX_DESIGN_PMON_CH0_EN |
false |
PHY_TERM_X_R_S_AC_OUTPUT_OHM |
SERIES_34_OHM_CAL |
PHY_TERM_X_R_S_CK_OUTPUT_OHM |
SERIES_34_OHM_CAL |
PHY_TERM_X_R_S_DQ_OUTPUT_OHM |
SERIES_34_OHM_CAL |
PHY_TERM_X_DQ_SLEW_RATE |
FASTEST |
PHY_TERM_X_R_T_DQ_INPUT_OHM |
RT_50_OHM_CAL |
PHY_TERM_X_DQ_VREF |
68.3 |
PHY_TERM_X_R_T_REFCLK_INPUT_OHM |
RT_DIFF |
MEM_ODT_DQ_X_TGT_WR |
4 |
MEM_ODT_DQ_X_NON_TGT_WR |
off |
MEM_ODT_DQ_X_NON_TGT_RD |
off |
MEM_ODT_DQ_X_RON |
7 |
MEM_VREF_DQ_X_RANGE |
2 |
MEM_VREF_DQ_X_VALUE |
67.75 |
ANALOG_PARAM_DERIVATION_PARAM_NAME |
|
deviceFamily |
UNKNOWN |
generateLegacySim |
false |