MEM_TECHNOLOGY_AUTO_BOOL |
false |
MEM_TECHNOLOGY |
MEM_TECHNOLOGY_DDR4 |
HPS_EMIF_CONFIG_AUTO_BOOL |
false |
HPS_EMIF_CONFIG |
HPS_EMIF_1x32 |
MEM_FORMAT |
MEM_FORMAT_DISCRETE |
MEM_TOPOLOGY |
MEM_TOPOLOGY_FLYBY |
MEM_NUM_RANKS |
1 |
MEM_NUM_CHANNELS |
1 |
MEM_DEVICE_DQ_WIDTH |
16 |
MEM_COMPS_PER_RANK |
2 |
MEM_AC_MIRRORING_AUTO_BOOL |
true |
MEM_AC_MIRRORING_AUTO |
false |
CTRL_ECC_MODE_AUTO_BOOL |
true |
CTRL_ECC_MODE_AUTO |
CTRL_ECC_MODE_DISABLED |
MEM_TOTAL_DQ_WIDTH |
32 |
PHY_AC_PLACEMENT_AUTO_BOOL |
false |
PHY_AC_PLACEMENT |
PHY_AC_PLACEMENT_BOT |
PHY_ALERT_N_PLACEMENT |
PHY_ALERT_N_PLACEMENT_AC2 |
USER_MIN_NUM_AC_LANES |
3 |
PHY_MEMCLK_FREQ_MHZ_AUTO_BOOL |
false |
PHY_MEMCLK_FREQ_MHZ |
800.0 |
MEM_PRESET_FILE_EN |
true |
MEM_PRESET_FILE_QPRS |
/nfs/site/disks/swbld_ops_7/users/jenkins-ghrd-smnode/workspace/Embedded/ghrd-sm/sm7_mod_som_baseline_6s/24.2/atgit/build/tmp.tjdBiHai3B/applications.fpga.soc.ghrd-socfpga/agilex5_soc_devkit_ghrd/board/preset_files/ddr4/DDR4-1600L_800MHz_CL12_alloff_component_1CS_DDP_32Gb_2Gx16.qprs |
MEM_PRESET_ID_AUTO_BOOL |
false |
MEM_PRESET_ID |
DDR4-1600L_800MHz_CL12_alloff_component_1CS_DDP_32Gb_2Gx16 |
PHY_REFCLK_FREQ_MHZ_AUTO_BOOL |
false |
PHY_REFCLK_FREQ_MHZ |
150.0 |
PHY_IO_VOLTAGE |
1.2 |
GRP_PHY_AC_AUTO_BOOL |
true |
GRP_PHY_AC_X_R_S_AC_OUTPUT_OHM_AUTO |
RTT_PHY_OUT_34_CAL |
GRP_PHY_CLK_AUTO_BOOL |
true |
GRP_PHY_CLK_X_R_S_CK_OUTPUT_OHM_AUTO |
RTT_PHY_OUT_34_CAL |
GRP_PHY_DATA_AUTO_BOOL |
true |
GRP_PHY_DATA_X_DQ_IO_STD_TYPE_AUTO |
PHY_IO_STD_TYPE_POD |
GRP_PHY_DATA_X_R_S_DQ_OUTPUT_OHM_AUTO |
RTT_PHY_OUT_34_CAL |
GRP_PHY_DATA_X_DQ_SLEW_RATE_AUTO |
PHY_SLEW_RATE_FASTEST |
GRP_PHY_DATA_X_R_T_DQ_INPUT_OHM_AUTO |
RTT_PHY_IN_50_CAL |
GRP_PHY_DATA_X_DQ_VREF_AUTO |
68.3 |
GRP_PHY_IN_AUTO_BOOL |
true |
GRP_PHY_IN_X_R_T_REFCLK_INPUT_OHM_AUTO |
LVDS_DIFF_TERM_ON |
GRP_PHY_DFE_AUTO_BOOL |
true |
GRP_MEM_ODT_DQ_AUTO_BOOL |
true |
GRP_MEM_ODT_DQ_X_TGT_WR_AUTO |
MEM_RTT_COMM_4 |
GRP_MEM_ODT_DQ_X_RON_AUTO |
MEM_DRIVE_STRENGTH_7 |
GRP_MEM_DQ_VREF_AUTO_BOOL |
true |
GRP_MEM_DQ_VREF_X_RANGE_AUTO |
MEM_VREF_RANGE_DDR4_2 |
GRP_MEM_DQ_VREF_X_VALUE_AUTO |
67.75 |
GRP_MEM_ODT_CA_AUTO_BOOL |
true |
GRP_MEM_VREF_CA_AUTO_BOOL |
true |
GRP_MEM_DFE_AUTO_BOOL |
true |
USER_EXTRA_PARAMETERS |
BYTE_SWIZZLE_CH0=0,X,X,X,1,2,3,X;PIN_SWIZZLE_CH0_DQS3=26,30,28,24,25,27,29,31;PIN_SWIZZLE_CH0_DQS2=16,20,22,18,23,21,19,17;PIN_SWIZZLE_CH0_DQS1=14,11,12,8,10,9,13,15;PIN_SWIZZLE_CH0_DQS0=2,0,6,4,7,5,3,1; |
DEBUG_TOOLS_EN |
false |
AXI_SIDEBAND_ACCESS_MODE_AUTO_BOOL |
true |
AXI_SIDEBAND_ACCESS_MODE_AUTO |
NOC |
INSTANCE_ID_IP0 |
0 |
EX_DESIGN_HDL_FORMAT |
HDL_FORMAT_VERILOG |
EX_DESIGN_GEN_SYNTH |
true |
EX_DESIGN_GEN_SIM |
true |
EX_DESIGN_CORE_CLK_FREQ_MHZ_AUTO_BOOL |
true |
EX_DESIGN_CORE_CLK_FREQ_MHZ_AUTO |
200 |
EX_DESIGN_CORE_REFCLK_FREQ_MHZ |
100 |
EX_DESIGN_HYDRA_REMOTE |
CONFIG_INTF_MODE_REMOTE_JTAG |
EX_DESIGN_PMON_ENABLED |
false |
EX_DESIGN_HYDRA_PROG |
emif_tg_emulation |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |