From 1aa89dfb8b84f2329f3edafdb829e6ab27f9c257 Mon Sep 17 00:00:00 2001
From: "Teoh, Ji Sheng" <ji.sheng.teoh@intel.com>
Date: Thu, 11 Nov 2021 19:10:12 +0000
Subject: [PATCH] socfpga_stratix10_socdk: include combined ghrd design

Signed-off-by: Teoh, Ji Sheng <ji.sheng.teoh@intel.com>
---
 .../boot/dts/altera/socfpga_stratix10.dtsi    |   3 +
 ...socfpga_stratix10_qse_pcie_sgmii_ghrd.dtsi | 245 ++++++++++++++++++
 ...ga_stratix10_qse_pcie_sgmii_ghrd_nand.dtsi | 245 ++++++++++++++++++
 .../dts/altera/socfpga_stratix10_socdk.dts    |   2 +-
 .../altera/socfpga_stratix10_socdk_nand.dts   |   1 +
 5 files changed, 495 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm64/boot/dts/altera/socfpga_stratix10_qse_pcie_sgmii_ghrd.dtsi
 create mode 100644 arch/arm64/boot/dts/altera/socfpga_stratix10_qse_pcie_sgmii_ghrd_nand.dtsi

diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
index 1410956e56f4..60cdd9419751 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
@@ -145,6 +145,7 @@
 			mac-address = [00 00 00 00 00 00];
 			resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
 			reset-names = "stmmaceth", "stmmaceth-ocp";
+			#clock-cells = <1>;
 			clocks = <&clkmgr STRATIX10_EMAC0_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>;
 			clock-names = "stmmaceth", "ptp_ref";
 			tx-fifo-depth = <16384>;
@@ -163,6 +164,7 @@
 			mac-address = [00 00 00 00 00 00];
 			resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
 			reset-names = "stmmaceth", "stmmaceth-ocp";
+			#clock-cells = <1>;
 			clocks = <&clkmgr STRATIX10_EMAC1_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>;
 			clock-names = "stmmaceth", "ptp_ref";
 			tx-fifo-depth = <16384>;
@@ -181,6 +183,7 @@
 			mac-address = [00 00 00 00 00 00];
 			resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
 			reset-names = "stmmaceth", "stmmaceth-ocp";
+			#clock-cells = <1>;
 			clocks = <&clkmgr STRATIX10_EMAC2_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>;
 			clock-names = "stmmaceth", "ptp_ref";
 			tx-fifo-depth = <16384>;
diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_qse_pcie_sgmii_ghrd.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10_qse_pcie_sgmii_ghrd.dtsi
new file mode 100644
index 000000000000..7b3894e46762
--- /dev/null
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_qse_pcie_sgmii_ghrd.dtsi
@@ -0,0 +1,245 @@
+/*
+* Add this piece of dtsi fragment as #include "socfpga_stratix10_qse.dtsi"
+* in the file socfpga_stratix10_socdk.dts. Compile it in the kernel along with
+* socfpga_stratix10.dtsi.
+*/
+
+/{
+	soc {
+		led_pio: gpio@f9001080 {
+				compatible = "altr,pio-1.0";
+				reg = <0xf9001080 0x8>;
+				altr,gpio-bank-width = <4>;
+				#gpio-cells = <2>;
+				gpio-controller;
+				resetvalue = <0>;
+		};
+
+		button_pio: gpio@f9001060 {
+				compatible = "altr,pio-1.0";
+				reg = <0xf9001060 0x10>;
+				interrupt-parent = <&intc>;
+				interrupts = <0 18 4>;
+				altr,gpio-bank-width = <4>;
+				altr,interrupt-type = <2>;
+				#gpio-cells = <2>;
+				gpio-controller;
+		};
+
+		dipsw_pio: gpio@f9001070 {
+				compatible = "altr,pio-1.0";
+				reg = <0xf9001070 0x10>;
+				interrupt-parent = <&intc>;
+				interrupts = <0 17 4>;
+				altr,gpio-bank-width = <4>;
+				altr,interrupt-type = <3>;
+				#gpio-cells = <2>;
+				gpio-controller;
+		};
+
+		trigger_pio: gpio@f9001040 {
+				compatible = "altr,pio-1.0";
+				reg = <0xf9001040 0x20>;
+				altr,gpio-bank-width = <4>;
+				#gpio-cells = <2>;
+				gpio-controller;
+				resetvalue = <0>;
+		};
+
+		soc_leds: leds {
+			compatible = "gpio-leds";
+
+			led_fpga0: fpga0 {
+					label = "fpga_led0";
+					gpios = <&led_pio 0 0>;
+			}; //end fpga0 (led_fpga0)
+
+			led_fpga1: fpga1 {
+					label = "fpga_led1";
+					gpios = <&led_pio 1 0>;
+			}; //end fpga1 (led_fpga1)
+
+			led_fpga2: fpga2 {
+					label = "fpga_led2";
+					gpios = <&led_pio 2 0>;
+			}; //end fpga2 (led_fpga2)
+
+			led_fpga3: fpga3 {
+					label = "fpga_led3";
+					gpios = <&led_pio 3 0>;
+			}; //end fpga3 (led_fpga3)
+		};
+
+		clocks {
+			ptp_ctrl_10G_clk: ptp_ctrl_10G_clk {
+				#clock-cells = <0>;
+				compatible = "fixed-clock";
+				clock-frequency = <312500000>;
+				clock-output-names = "ptp_ctrl_10G_clk-clk";
+			};
+
+			sgmii_1_clk_0: sgmii_1_clk_0 {
+				compatible = "fixed-clock";
+				#clock-cells = <0>;
+				clock-frequency = <125000000>;	/* 125.00 MHz */
+				clock-output-names = "sgmii_1_clk_0-out_clk";
+			}; //end sgmii_1_clk_0 (sgmii_1_clk_0)
+
+			sgmii_1_clk_125: sgmii_1_clk_125 {
+				compatible = "fixed-clock";
+				#clock-cells = <0>;
+				clock-frequency = <125000000>;	/* 125.00 MHz */
+				clock-output-names = "sgmii_1_clk_125-out_clk";
+			}; //end sgmii_1_clk_125 (sgmii_1_clk_125)
+
+			sgmii_2_clk_0: sgmii_2_clk_0 {
+				compatible = "fixed-clock";
+				#clock-cells = <0>;
+				clock-frequency = <125000000>;	/* 125.00 MHz */
+				clock-output-names = "sgmii_2_clk_0-out_clk";
+			}; //end sgmii_2_clk_0 (sgmii_2_clk_0)
+
+			sgmii_2_clk_125: sgmii_2_clk_125 {
+				compatible = "fixed-clock";
+				#clock-cells = <0>;
+				clock-frequency = <125000000>;	/* 125.00 MHz */
+				clock-output-names = "sgmii_2_clk_125-out_clk";
+			}; //end sgmii_2_clk_125 (sgmii_2_clk_125)
+		};
+
+		i2c0: i2c@ffc02800 {
+			status = "okay";
+		};
+
+		s10_hps_bridges: bridge@80000000 {
+			compatible = "altr,bridge-18.1","simple-bus";
+			reg = <0x80000000 0x60000000>,
+				<0xf9000000 0x00100000>;
+			reg-names = "axi_h2f", "axi_h2f_lw";
+			#address-cells = <0x2>;
+			#size-cells = <0x1>;
+			ranges = <0x00000000 0x00000000 0x80000000 0x00040000>,
+				<0x00000000 0x10000000 0x90000000 0x10000000>,
+				<0x00000000 0x20000000 0xa0000000 0x00200000>,
+				<0x00000001 0x00010000 0xf9010000 0x00008000>,
+				<0x00000001 0x00018000 0xf9018000 0x00000080>,
+				<0x00000001 0x00018080 0xf9018080 0x00000010>,
+				<0x00000001 0x00020000 0xf9020000 0x00001000>,
+				<0x00000001 0x00022000 0xf9022000 0x00002000>,
+				<0x00000001 0x00026000 0xf9026000 0x00000040>,
+				<0x00000001 0x00002020 0xf9002020 0x00000020>,
+				<0x00000001 0x00002000 0xf9002000 0x00000020>,
+				<0x00000001 0x00002120 0xf9002120 0x00000020>,
+				<0x00000001 0x00002100 0xf9002100 0x00000020>,
+				<0x00000001 0x00002140 0xf9002140 0x00000020>,
+				<0x00000001 0x00030100 0xf9030100 0x00000010>,
+				<0x00000001 0x00000300 0xf9000300 0x00000010>,
+				<0x00000001 0x00000310 0xf9000310 0x00000010>,
+				<0x00000001 0x00003000 0xf9003000 0x00000040>,
+				<0x00000001 0x00003040 0xf9003040 0x00000008>,
+				<0x00000001 0x00003080 0xf9003080 0x00000040>,
+				<0x00000001 0x000030c0 0xf90030c0 0x00000008>;
+
+			sgmii_1_gmii2sgmii: sgmii1@0x100003000 {
+				compatible = "altr,gmii-to-sgmii-2.0";
+				reg = <0x00000001 0x00003000 0x00000040>,
+				      <0x00000001 0x00003040 0x00000008>;
+				reg-names = "eth_tse_control_port", "gmii_to_sgmii_adapter_avalon_slave";
+				clocks = <&sgmii_1_clk_0 &gmac1 1 &sgmii_1_clk_125 &sgmii_1_clk_125>;
+				clock-names = "clock_in", "emac_gtx_clk", "tse_pcs_ref_clk_clock_connection", "tse_rx_cdr_refclk";
+			};
+
+			sgmii_2_gmii2sgmii: sgmii2@100003080 {
+				compatible = "altr,gmii-to-sgmii-2.0";
+				reg = <0x00000001 0x00003080 0x00000040>,
+					<0x00000001 0x000030c0 0x00000008>;
+				reg-names = "eth_tse_control_port", "gmii_to_sgmii_adapter_avalon_slave";
+				clocks = <&sgmii_2_clk_0 &gmac2 1 &sgmii_2_clk_125 &sgmii_2_clk_125>;
+				clock-names = "clock_in", "emac_gtx_clk", "tse_pcs_ref_clk_clock_connection", "tse_rx_cdr_refclk";
+			};
+
+			qse_0_qse: ethernet@100020000 {
+				compatible = "altr,qse-msgdma-2.0";
+				reg-names = "control_port", "xcvr_ctrl", "tod_ctrl",
+						"tx_csr", "tx_pref", "rx_csr", "rx_pref",
+						"rx_fifo", "phy_reconfig_csr";
+				reg = <0x00000001 0x00020000 0x00001000>,
+					<0x00000001 0x00022000 0x00002000>,
+					<0x00000001 0x00026000 0x00000040>,
+					<0x00000001 0x00002020 0x00000020>,
+					<0x00000001 0x00002000 0x00000020>,
+					<0x00000001 0x00002120 0x00000020>,
+					<0x00000001 0x00002100 0x00000020>,
+					<0x00000001 0x00002140 0x00000020>,
+					<0x00000001 0x00030100 0x00000010>;
+				dma-coherent;
+				phy-mode = "10gbase-kr";
+				sfp = <&sfp_eth0>;
+				clocks = <&ptp_ctrl_10G_clk>;
+				clock-names = "tod_clk";
+				interrupt-parent = <&intc>;
+				interrupt-names = "tx_irq", "rx_irq";
+				interrupts = <0 21 4>,
+						<0 22 4>;
+				rx-fifo-depth = <0x20000>;
+				tx-fifo-depth = <0x1000>;
+				rx-fifo-almost-full = <0x10000>;
+				rx-fifo-almost-empty = <0x8000>;
+				local-mac-address = [00 00 00 00 00 00];
+				altr,tx-pma-delay-ns = <0xD>;
+				altr,rx-pma-delay-ns = <0x8>;
+				altr,tx-pma-delay-fns = <0x24D>;
+				altr,rx-pma-delay-fns = <0x3E97>;
+				altr,has-ptp;
+				status = "okay";
+			};
+
+			sfp_eth0: sfp-eth0 {
+				compatible = "sff,sfp";
+				i2c-bus = <&i2c0>;
+				los-gpio = <&mge_10g_status_pio 0 GPIO_ACTIVE_HIGH>;
+				mod-def0-gpio = <&mge_10g_status_pio 2 GPIO_ACTIVE_LOW>;
+				maximum-power-milliwatt = <1000>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&sfp_ctrl_pio &mge_10g_status_pio>;
+				tx-disable-gpio = <&sfp_ctrl_pio 0 GPIO_ACTIVE_HIGH>;
+				tx-fault-gpio = <&mge_10g_status_pio 1 GPIO_ACTIVE_HIGH>;
+				rate-select0-gpio = <&sfp_ctrl_pio 2 GPIO_ACTIVE_HIGH>;
+			};
+
+			sfp_ctrl_pio: gpio@100000300 {
+				compatible = "altr,pio-1.0";
+				reg = <0x00000001 0x00000300 0x10>;
+				interrupt-parent = <&intc>;
+				interrupts = <0 23 4>;
+				altr,gpio-bank-width = <4>;
+				altr,interrupt-type = <2>;
+				#gpio-cells = <2>;
+				gpio-controller;
+			};
+
+			mge_10g_status_pio: gpio@100000310 {
+				compatible = "altr,pio-1.0";
+				reg = <0x00000001 0x00000310 0x10>;
+				interrupt-parent = <&intc>;
+				interrupts = <0 24 4>;
+				altr,gpio-bank-width = <4>;
+				altr,interrupt-type = <2>;
+				#gpio-cells = <2>;
+				gpio-controller;
+			};
+		};
+	};
+};
+
+&gmac1 {
+	altr,gmii-to-sgmii-converter = <&sgmii_1_gmii2sgmii>;
+	phy-mode = "sgmii";
+	status = "okay";
+};
+
+&gmac2 {
+	altr,gmii-to-sgmii-converter = <&sgmii_2_gmii2sgmii>;
+	phy-mode = "sgmii";
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_qse_pcie_sgmii_ghrd_nand.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10_qse_pcie_sgmii_ghrd_nand.dtsi
new file mode 100644
index 000000000000..1fc639b36c4c
--- /dev/null
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_qse_pcie_sgmii_ghrd_nand.dtsi
@@ -0,0 +1,245 @@
+/*
+* Add this piece of dtsi fragment as #include "socfpga_stratix10_qse.dtsi"
+* in the file socfpga_stratix10_socdk.dts. Compile it in the kernel along with
+* socfpga_stratix10.dtsi.
+*/
+
+/{
+	soc {
+		led_pio: gpio@f9001080 {
+				compatible = "altr,pio-1.0";
+				reg = <0xf9001080 0x8>;
+				altr,gpio-bank-width = <4>;
+				#gpio-cells = <2>;
+				gpio-controller;
+				resetvalue = <0>;
+		};
+
+		button_pio: gpio@f9001060 {
+				compatible = "altr,pio-1.0";
+				reg = <0xf9001060 0x10>;
+				interrupt-parent = <&intc>;
+				interrupts = <0 18 4>;
+				altr,gpio-bank-width = <4>;
+				altr,interrupt-type = <2>;
+				#gpio-cells = <2>;
+				gpio-controller;
+		};
+
+		dipsw_pio: gpio@f9001070 {
+				compatible = "altr,pio-1.0";
+				reg = <0xf9001070 0x10>;
+				interrupt-parent = <&intc>;
+				interrupts = <0 17 4>;
+				altr,gpio-bank-width = <4>;
+				altr,interrupt-type = <3>;
+				#gpio-cells = <2>;
+				gpio-controller;
+		};
+
+		trigger_pio: gpio@f9001040 {
+				compatible = "altr,pio-1.0";
+				reg = <0xf9001040 0x20>;
+				altr,gpio-bank-width = <4>;
+				#gpio-cells = <2>;
+				gpio-controller;
+				resetvalue = <0>;
+		};
+
+		soc_leds: leds {
+			compatible = "gpio-leds";
+
+			led_fpga0: fpga0 {
+					label = "fpga_led0";
+					gpios = <&led_pio 0 0>;
+			}; //end fpga0 (led_fpga0)
+
+			led_fpga1: fpga1 {
+					label = "fpga_led1";
+					gpios = <&led_pio 1 0>;
+			}; //end fpga1 (led_fpga1)
+
+			led_fpga2: fpga2 {
+					label = "fpga_led2";
+					gpios = <&led_pio 2 0>;
+			}; //end fpga2 (led_fpga2)
+
+			led_fpga3: fpga3 {
+					label = "fpga_led3";
+					gpios = <&led_pio 3 0>;
+			}; //end fpga3 (led_fpga3)
+		};
+
+		clocks {
+			ptp_ctrl_10G_clk: ptp_ctrl_10G_clk {
+				#clock-cells = <0>;
+				compatible = "fixed-clock";
+				clock-frequency = <312500000>;
+				clock-output-names = "ptp_ctrl_10G_clk-clk";
+			};
+
+			sgmii_1_clk_0: sgmii_1_clk_0 {
+				compatible = "fixed-clock";
+				#clock-cells = <0>;
+				clock-frequency = <125000000>;	/* 125.00 MHz */
+				clock-output-names = "sgmii_1_clk_0-out_clk";
+			}; //end sgmii_1_clk_0 (sgmii_1_clk_0)
+
+			sgmii_1_clk_125: sgmii_1_clk_125 {
+				compatible = "fixed-clock";
+				#clock-cells = <0>;
+				clock-frequency = <125000000>;	/* 125.00 MHz */
+				clock-output-names = "sgmii_1_clk_125-out_clk";
+			}; //end sgmii_1_clk_125 (sgmii_1_clk_125)
+
+			sgmii_2_clk_0: sgmii_2_clk_0 {
+				compatible = "fixed-clock";
+				#clock-cells = <0>;
+				clock-frequency = <125000000>;	/* 125.00 MHz */
+				clock-output-names = "sgmii_2_clk_0-out_clk";
+			}; //end sgmii_2_clk_0 (sgmii_2_clk_0)
+
+			sgmii_2_clk_125: sgmii_2_clk_125 {
+				compatible = "fixed-clock";
+				#clock-cells = <0>;
+				clock-frequency = <125000000>;	/* 125.00 MHz */
+				clock-output-names = "sgmii_2_clk_125-out_clk";
+			}; //end sgmii_2_clk_125 (sgmii_2_clk_125)
+		};
+
+		i2c0: i2c@ffc02800 {
+			status = "okay";
+		};
+
+		s10_hps_bridges: bridge@80000000 {
+			compatible = "altr,bridge-18.1","simple-bus";
+			reg = <0x80000000 0x60000000>,
+				<0xf9000000 0x00100000>;
+			reg-names = "axi_h2f", "axi_h2f_lw";
+			#address-cells = <0x2>;
+			#size-cells = <0x1>;
+			ranges = <0x00000000 0x00000000 0x80000000 0x00040000>,
+				<0x00000000 0x10000000 0x90000000 0x10000000>,
+				<0x00000000 0x20000000 0xa0000000 0x00200000>,
+				<0x00000001 0x00010000 0xf9010000 0x00008000>,
+				<0x00000001 0x00018000 0xf9018000 0x00000080>,
+				<0x00000001 0x00018080 0xf9018080 0x00000010>,
+				<0x00000001 0x00020000 0xf9020000 0x00001000>,
+				<0x00000001 0x00022000 0xf9022000 0x00002000>,
+				<0x00000001 0x00026000 0xf9026000 0x00000040>,
+				<0x00000001 0x00002020 0xf9002020 0x00000020>,
+				<0x00000001 0x00002000 0xf9002000 0x00000020>,
+				<0x00000001 0x00002120 0xf9002120 0x00000020>,
+				<0x00000001 0x00002100 0xf9002100 0x00000020>,
+				<0x00000001 0x00002140 0xf9002140 0x00000020>,
+				<0x00000001 0x00030100 0xf9030100 0x00000010>,
+				<0x00000001 0x00000300 0xf9000300 0x00000010>,
+				<0x00000001 0x00000310 0xf9000310 0x00000010>,
+				<0x00000001 0x00003000 0xf9003000 0x00000040>,
+				<0x00000001 0x00003040 0xf9003040 0x00000008>,
+				<0x00000001 0x00003080 0xf9003080 0x00000040>,
+				<0x00000001 0x000030c0 0xf90030c0 0x00000008>;
+
+			sgmii_1_gmii2sgmii: sgmii1@0x100003000 {
+				compatible = "altr,gmii-to-sgmii-2.0";
+				reg = <0x00000001 0x00003000 0x00000040>,
+				      <0x00000001 0x00003040 0x00000008>;
+				reg-names = "eth_tse_control_port", "gmii_to_sgmii_adapter_avalon_slave";
+				clocks = <&sgmii_1_clk_0 &gmac0 1 &sgmii_1_clk_125 &sgmii_1_clk_125>;
+				clock-names = "clock_in", "emac_gtx_clk", "tse_pcs_ref_clk_clock_connection", "tse_rx_cdr_refclk";
+			};
+
+			sgmii_2_gmii2sgmii: sgmii2@100003080 {
+				compatible = "altr,gmii-to-sgmii-2.0";
+				reg = <0x00000001 0x00003080 0x00000040>,
+					<0x00000001 0x000030c0 0x00000008>;
+				reg-names = "eth_tse_control_port", "gmii_to_sgmii_adapter_avalon_slave";
+				clocks = <&sgmii_2_clk_0 &gmac1 1 &sgmii_2_clk_125 &sgmii_2_clk_125>;
+				clock-names = "clock_in", "emac_gtx_clk", "tse_pcs_ref_clk_clock_connection", "tse_rx_cdr_refclk";
+			};
+
+			qse_0_qse: ethernet@100020000 {
+				compatible = "altr,qse-msgdma-2.0";
+				reg-names = "control_port", "xcvr_ctrl", "tod_ctrl",
+						"tx_csr", "tx_pref", "rx_csr", "rx_pref",
+						"rx_fifo", "phy_reconfig_csr";
+				reg = <0x00000001 0x00020000 0x00001000>,
+					<0x00000001 0x00022000 0x00002000>,
+					<0x00000001 0x00026000 0x00000040>,
+					<0x00000001 0x00002020 0x00000020>,
+					<0x00000001 0x00002000 0x00000020>,
+					<0x00000001 0x00002120 0x00000020>,
+					<0x00000001 0x00002100 0x00000020>,
+					<0x00000001 0x00002140 0x00000020>,
+					<0x00000001 0x00030100 0x00000010>;
+				dma-coherent;
+				phy-mode = "10gbase-kr";
+				sfp = <&sfp_eth0>;
+				clocks = <&ptp_ctrl_10G_clk>;
+				clock-names = "tod_clk";
+				interrupt-parent = <&intc>;
+				interrupt-names = "tx_irq", "rx_irq";
+				interrupts = <0 21 4>,
+						<0 22 4>;
+				rx-fifo-depth = <0x20000>;
+				tx-fifo-depth = <0x1000>;
+				rx-fifo-almost-full = <0x10000>;
+				rx-fifo-almost-empty = <0x8000>;
+				local-mac-address = [00 00 00 00 00 00];
+				altr,tx-pma-delay-ns = <0xD>;
+				altr,rx-pma-delay-ns = <0x8>;
+				altr,tx-pma-delay-fns = <0x24D>;
+				altr,rx-pma-delay-fns = <0x3E97>;
+				altr,has-ptp;
+				status = "okay";
+			};
+
+			sfp_eth0: sfp-eth0 {
+				compatible = "sff,sfp";
+				i2c-bus = <&i2c0>;
+				los-gpio = <&mge_10g_status_pio 0 GPIO_ACTIVE_HIGH>;
+				mod-def0-gpio = <&mge_10g_status_pio 2 GPIO_ACTIVE_LOW>;
+				maximum-power-milliwatt = <1000>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&sfp_ctrl_pio &mge_10g_status_pio>;
+				tx-disable-gpio = <&sfp_ctrl_pio 0 GPIO_ACTIVE_HIGH>;
+				tx-fault-gpio = <&mge_10g_status_pio 1 GPIO_ACTIVE_HIGH>;
+				rate-select0-gpio = <&sfp_ctrl_pio 2 GPIO_ACTIVE_HIGH>;
+			};
+
+			sfp_ctrl_pio: gpio@100000300 {
+				compatible = "altr,pio-1.0";
+				reg = <0x00000001 0x00000300 0x10>;
+				interrupt-parent = <&intc>;
+				interrupts = <0 23 4>;
+				altr,gpio-bank-width = <4>;
+				altr,interrupt-type = <2>;
+				#gpio-cells = <2>;
+				gpio-controller;
+			};
+
+			mge_10g_status_pio: gpio@100000310 {
+				compatible = "altr,pio-1.0";
+				reg = <0x00000001 0x00000310 0x10>;
+				interrupt-parent = <&intc>;
+				interrupts = <0 24 4>;
+				altr,gpio-bank-width = <4>;
+				altr,interrupt-type = <2>;
+				#gpio-cells = <2>;
+				gpio-controller;
+			};
+		};
+	};
+};
+
+&gmac0 {
+	altr,gmii-to-sgmii-converter = <&sgmii_1_gmii2sgmii>;
+	phy-mode = "sgmii";
+	status = "okay";
+};
+
+&gmac1 {
+	altr,gmii-to-sgmii-converter = <&sgmii_2_gmii2sgmii>;
+	phy-mode = "sgmii";
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
index 4019f176a23f..0df18c0c7674 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
@@ -4,7 +4,7 @@
  */
 
 #include "socfpga_stratix10.dtsi"
-#include "socfpga_stratix10_qse.dtsi"
+#include "socfpga_stratix10_qse_pcie_sgmii_ghrd.dtsi"
 
 / {
 	model = "SoCFPGA Stratix 10 SoCDK";
diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts
index bbc3db42d6e8..339f38229704 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts
@@ -4,6 +4,7 @@
  */
 
 #include "socfpga_stratix10.dtsi"
+#include "socfpga_stratix10_qse_pcie_sgmii_ghrd_nand.dtsi"
 
 / {
 	model = "SoCFPGA Stratix 10 SoCDK";
-- 
2.17.1

