From fb5e797b3a21a6f93e31be6bc2ed2680b22ef052 Mon Sep 17 00:00:00 2001
From: "Chew, Chiau Ee" <chiau.ee.chew@intel.com>
Date: Thu, 25 Feb 2021 19:20:53 +0800
Subject: [PATCH] socfpga_arria10_socdk: tse: include reference design dtsi

Signed-off-by: Chew, Chiau Ee <chiau.ee.chew@intel.com>
---
 arch/arm/boot/dts/socfpga_arria10_socdk.dtsi |   1 +
 arch/arm/boot/dts/socfpga_arria10_tse.dtsi   | 150 +++++++++++++++++++
 2 files changed, 151 insertions(+)
 create mode 100644 arch/arm/boot/dts/socfpga_arria10_tse.dtsi

diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
index 1ff37b89b109..cc521f0a9bd8 100644
--- a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
@@ -3,6 +3,7 @@
  * Copyright (C) 2015 Altera Corporation <www.altera.com>
  */
 #include "socfpga_arria10.dtsi"
+#include "socfpga_arria10_tse.dtsi"
 
 / {
 	model = "Altera SOCFPGA Arria 10";
diff --git a/arch/arm/boot/dts/socfpga_arria10_tse.dtsi b/arch/arm/boot/dts/socfpga_arria10_tse.dtsi
new file mode 100644
index 000000000000..bf7988d819a7
--- /dev/null
+++ b/arch/arm/boot/dts/socfpga_arria10_tse.dtsi
@@ -0,0 +1,150 @@
+/*
+* Add this piece of dtsi fragment as #include "socfpga_arria10_tse.dtsi"
+* in the file socfpga_arria10_socdk.dtsi. Compile it in the kernel along with
+* socfpga_arria10.dtsi.
+*/
+
+/{
+	soc {
+		clkmgr@ffd04000 {
+			clocks {
+				clk_100: clk_100 {
+					compatible = "fixed-clock";
+					#clock-cells = <0>;
+					clock-frequency = <100000000>;  /* 100.00 MHz */
+					clock-output-names = "clk_100-out_clk";
+				}; //end clk_100 (clk_100)
+
+				tse_0_refclk_125: tse_0_refclk_125 {
+					compatible = "fixed-clock";
+					#clock-cells = <0>;
+					clock-frequency = <125000000>;  /* 125.00 MHz */
+					clock-output-names = "tse_0_refclk_125-out_clk";
+				}; //end tse_0_refclk_125 (tse_0_refclk_125)
+
+				tse_0_tse_clk: tse_0_tse_clk {
+					compatible = "fixed-clock";
+					#clock-cells = <0>;
+					clock-frequency = <100000000>;  /* 100.00 MHz */
+					clock-output-names = "tse_0_tse_clk-out_clk";
+				}; //end tse_0_tse_clk (tse_0_tse_clk)
+
+				tse_1_refclk_125: tse_1_refclk_125 {
+					compatible = "fixed-clock";
+					#clock-cells = <0>;
+					clock-frequency = <125000000>;  /* 125.00 MHz */
+					clock-output-names = "tse_1_refclk_125-out_clk";
+				}; //end tse_1_refclk_125 (tse_1_refclk_125)
+
+				tse_1_tse_clk: tse_1_tse_clk {
+					compatible = "fixed-clock";
+					#clock-cells = <0>;
+					clock-frequency = <100000000>;  /* 100.00 MHz */
+					clock-output-names = "tse_1_tse_clk-out_clk";
+				}; //end tse_1_tse_clk (tse_1_tse_clk)
+			};
+		};
+
+		a10_hps_bridges: bridge@0xc0000000 {
+			compatible = "altr,bridge-19.1", "simple-bus";
+			reg = <0xc0000000 0x20000000>,
+				<0xff200000 0x00200000>;
+			reg-names = "axi_h2f", "axi_h2f_lw";
+			clocks = <&clk_100 &clk_100 &clk_100 &clk_100>;
+			clock-names = "h2f_axi_clock", "h2f_lw_axi_clock", "f2sdram0_clock", "f2sdram2_clock";
+			#address-cells = <2>;
+			#size-cells = <1>;
+			ranges = <0x00000001 0x00001000 0xff201000 0x00000400>,
+				<0x00000001 0x00001460 0xff201460 0x00000020>,
+				<0x00000001 0x00001400 0xff201400 0x00000020>,
+				<0x00000001 0x00001480 0xff201480 0x00000020>,
+				<0x00000001 0x00001420 0xff201420 0x00000020>,
+				<0x00000001 0x00001440 0xff201440 0x00000008>,
+				<0x00000001 0x00001800 0xff201800 0x00000400>,
+				<0x00000001 0x00001c60 0xff201c60 0x00000020>,
+				<0x00000001 0x00001c00 0xff201c00 0x00000020>,
+				<0x00000001 0x00001c80 0xff201c80 0x00000020>,
+				<0x00000001 0x00001c20 0xff201c20 0x00000020>,
+				<0x00000001 0x00001c40 0xff201c40 0x00000008>;
+
+			tse_0_tse: ethernet@0x100001000 {
+				compatible = "altr,tse-msgdma-19.1", "altr,tse-msgdma-1.0", "altr,tse-1.0";
+				reg = <0x00000001 0x00001000 0x00000400>,
+					<0x00000001 0x00001400 0x00000020>,
+					<0x00000001 0x00001420 0x00000020>,
+					<0x00000001 0x00001440 0x00000008>,
+					<0x00000001 0x00001460 0x00000020>,
+					<0x00000001 0x00001480 0x00000020>;
+				reg-names = "control_port", "rx_csr", "rx_desc", "rx_resp", "tx_csr", "tx_desc";
+				interrupt-parent = <&intc>;
+				interrupts = <0 21 4 0 22 4>;
+				interrupt-names = "rx_irq", "tx_irq";
+				clocks = <&tse_0_tse_clk &tse_0_tse_clk &tse_0_tse_clk &tse_0_refclk_125 &tse_0_refclk_125>;
+				clock-names = "transmit_clock_connection", "receive_clock_connection", "control_port_clock_connection", "pcs_ref_clk_clock_connection", "rx_cdr_refclk";
+				ALTR,rx-fifo-depth = <2048>;    /* embeddedsw.dts.params.ALTR,rx-fifo-depth type NUMBER */
+				ALTR,tx-fifo-depth = <2048>;    /* embeddedsw.dts.params.ALTR,tx-fifo-depth type NUMBER */
+				phy-mode = "sgmii";     /* embeddedsw.dts.params.phy-mode type STRING */
+				rx-fifo-depth = <8192>; /* embeddedsw.dts.params.rx-fifo-depth type NUMBER */
+				tx-fifo-depth = <8192>; /* embeddedsw.dts.params.tx-fifo-depth type NUMBER */
+				address-bits = <48>;
+				max-frame-size = <1518>;
+				local-mac-address = [00 00 00 00 00 00];
+				altr,enable-sup-addr = <0>;
+				altr,enable-hash = <0>;
+				phy-addr = <0>;
+				ALTR,phy-addr = <0>;
+
+				tse_0_tse_mdio: mdio {
+					compatible = "altr,tse-mdio";
+					#address-cells = <1>;
+					#size-cells = <0>;
+					phy-handle = <&tse_0_tse_phy>;
+
+					tse_0_tse_phy: phy {
+						reg = <0x00000000>;
+					}; //end phy (tse_0_tse_phy)
+				}; //end mdio (tse_0_tse_mdio)
+			}; //end ethernet@0x100001000 (tse_0_tse)
+
+			tse_1_tse: ethernet@0x100001800 {
+				compatible = "altr,tse-msgdma-19.1", "altr,tse-msgdma-1.0", "altr,tse-1.0";
+				reg = <0x00000001 0x00001800 0x00000400>,
+					<0x00000001 0x00001c00 0x00000020>,
+					<0x00000001 0x00001c20 0x00000020>,
+					<0x00000001 0x00001c40 0x00000008>,
+					<0x00000001 0x00001c60 0x00000020>,
+					<0x00000001 0x00001c80 0x00000020>;
+				reg-names = "control_port", "rx_csr", "rx_desc", "rx_resp", "tx_csr", "tx_desc";
+				interrupt-parent = <&intc>;
+				interrupts = <0 23 4 0 24 4>;
+				interrupt-names = "rx_irq", "tx_irq";
+				clocks = <&tse_1_tse_clk &tse_1_tse_clk &tse_1_tse_clk &tse_1_refclk_125 &tse_1_refclk_125>;
+				clock-names = "transmit_clock_connection", "receive_clock_connection", "control_port_clock_connection", "pcs_ref_clk_clock_connection", "rx_cdr_refclk";
+				ALTR,rx-fifo-depth = <2048>;    /* embeddedsw.dts.params.ALTR,rx-fifo-depth type NUMBER */
+				ALTR,tx-fifo-depth = <2048>;    /* embeddedsw.dts.params.ALTR,tx-fifo-depth type NUMBER */
+				phy-mode = "sgmii";     /* embeddedsw.dts.params.phy-mode type STRING */
+				rx-fifo-depth = <8192>; /* embeddedsw.dts.params.rx-fifo-depth type NUMBER */
+				tx-fifo-depth = <8192>; /* embeddedsw.dts.params.tx-fifo-depth type NUMBER */
+				address-bits = <48>;
+				max-frame-size = <1518>;
+				local-mac-address = [00 00 00 00 00 00];
+				altr,enable-sup-addr = <0>;
+				altr,enable-hash = <0>;
+				phy-addr = <0>;
+				ALTR,phy-addr = <0>;
+
+				tse_1_tse_mdio: mdio {
+					compatible = "altr,tse-mdio";
+					#address-cells = <1>;
+					#size-cells = <0>;
+					phy-handle = <&tse_1_tse_phy>;
+
+					tse_1_tse_phy: phy {
+						reg = <0x00000000>;
+					}; //end phy (tse_1_tse_phy)
+				}; //end mdio (tse_1_tse_mdio)
+			}; //end ethernet@0x100001800 (tse_1_tse)
+		}; //end bridge@0xc0000000 (a10_hps_bridges)
+	};
+};
+
-- 
2.17.1

