From 7e4b45c12b7a16d9ca463c4532525cf94d85b6be Mon Sep 17 00:00:00 2001
From: "Teoh, Ji Sheng" <ji.sheng.teoh@intel.com>
Date: Fri, 12 Nov 2021 10:48:28 +0000
Subject: [PATCH] socfpga_agilex_socdk: include combined ghrd design

Signed-off-by: Teoh, Ji Sheng <ji.sheng.teoh@intel.com>
---
 arch/arm64/boot/dts/intel/socfpga_agilex.dtsi |   3 +
 .../dts/intel/socfpga_agilex_ghrd_sgmii.dtsi  | 124 ++++++++++++++++++
 .../boot/dts/intel/socfpga_agilex_socdk.dts   |   1 +
 .../dts/intel/socfpga_agilex_socdk_nand.dts   |   1 +
 4 files changed, 129 insertions(+)
 create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex_ghrd_sgmii.dtsi

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
index 44cf865ef824..56c5855e55b1 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
@@ -149,6 +149,7 @@
 			snps,multicast-filter-bins = <256>;
 			iommus = <&smmu 1>;
 			altr,sysmgr-syscon = <&sysmgr 0x44 0>;
+			#clock-cells = <1>;
 			clocks = <&clkmgr AGILEX_EMAC0_CLK>, <&clkmgr AGILEX_EMAC_PTP_CLK>;
 			clock-names = "stmmaceth", "ptp_ref";
 			status = "disabled";
@@ -167,6 +168,7 @@
 			snps,multicast-filter-bins = <256>;
 			iommus = <&smmu 2>;
 			altr,sysmgr-syscon = <&sysmgr 0x48 0>;
+			#clock-cells = <1>;
 			clocks = <&clkmgr AGILEX_EMAC1_CLK>, <&clkmgr AGILEX_EMAC_PTP_CLK>;
 			clock-names = "stmmaceth", "ptp_ref";
 			status = "disabled";
@@ -185,6 +187,7 @@
 			snps,multicast-filter-bins = <256>;
 			iommus = <&smmu 3>;
 			altr,sysmgr-syscon = <&sysmgr 0x4c 0>;
+			#clock-cells = <1>;
 			clocks = <&clkmgr AGILEX_EMAC2_CLK>, <&clkmgr AGILEX_EMAC_PTP_CLK>;
 			clock-names = "stmmaceth", "ptp_ref";
 			status = "disabled";
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_ghrd_sgmii.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex_ghrd_sgmii.dtsi
new file mode 100644
index 000000000000..31c77fd2e9b4
--- /dev/null
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex_ghrd_sgmii.dtsi
@@ -0,0 +1,124 @@
+/*
+* Add this piece of dtsi fragment as #include "socfpga_agilex_ghrd_sgmii.dtsi"
+* in the file socfpga_agilex_socdk.dts. Compile it in the kernel along with
+* socfpga_agilex.dtsi.
+*/
+
+/{
+	soc {
+
+		led_pio: gpio@f9001080 {
+				compatible = "altr,pio-1.0";
+				reg = <0xf9001080 0x8>;
+				altr,gpio-bank-width = <4>;
+				#gpio-cells = <2>;
+				gpio-controller;
+				resetvalue = <0>;
+		};
+
+		button_pio: gpio@f9001060 {
+				compatible = "altr,pio-1.0";
+				reg = <0xf9001060 0x10>;
+				interrupt-parent = <&intc>;	
+				interrupts = <0 18 4>;
+				altr,gpio-bank-width = <4>;
+				altr,interrupt-type = <2>;      
+                altr,interrupt_type = <2>;
+				#gpio-cells = <2>;
+				gpio-controller;
+		};
+
+		dipsw_pio: gpio@f9001070 {
+				compatible = "altr,pio-1.0";
+				reg = <0xf9001070 0x10>;
+				interrupt-parent = <&intc>;	
+				interrupts = <0 17 4>;
+				altr,gpio-bank-width = <4>;
+				altr,interrupt-type = <3>;      
+                altr,interrupt_type = <3>;
+				#gpio-cells = <2>;
+				gpio-controller;
+		};
+
+		trigger_pio: gpio@f9001040 {
+				compatible = "altr,pio-1.0";
+				reg = <0xf9001040 0x20>;
+				altr,gpio-bank-width = <4>;
+				#gpio-cells = <2>;
+				gpio-controller;
+				resetvalue = <0>;
+		};
+
+		soc_leds: leds {
+			compatible = "gpio-leds";
+
+			led_fpga0: fpga0 {
+					label = "fpga_led0";
+					gpios = <&led_pio 0 1>;
+			}; //end fpga0 (led_fpga0)
+
+			led_fpga1: fpga1 {
+					label = "fpga_led1";
+					gpios = <&led_pio 1 1>;
+			}; //end fpga1 (led_fpga1)
+
+			led_fpga2: fpga2 {
+					label = "fpga_led2";
+					gpios = <&led_pio 2 1>;
+			}; //end fpga2 (led_fpga2)
+
+			led_fpga3: fpga3 {
+					label = "fpga_led3";
+					gpios = <&led_pio 3 1>;
+			}; //end fpga3 (led_fpga3)
+		};
+		
+		clocks {
+			sgmii_1_clk_0: sgmii_1_clk_0 {
+                                compatible = "fixed-clock";
+                                #clock-cells = <0>;
+                                clock-frequency = <125000000>;  /* 125.00 MHz */
+                                clock-output-names = "sgmii_1_clk_0-out_clk";
+                        }; //end sgmii_1_clk_0 (sgmii_1_clk_0)
+
+            sgmii_1_clk_125: sgmii_1_clk_125 {
+                                compatible = "fixed-clock";
+                                #clock-cells = <0>;
+                                clock-frequency = <125000000>;  /* 125.00 MHz */
+                                clock-output-names = "sgmii_1_clk_125-out_clk";
+                        }; //end sgmii_1_clk_125 (sgmii_1_clk_125)
+		};
+		
+		s10_hps_bridges: bridge@80000000 {
+                        compatible = "altr,bridge-18.1", "simple-bus";
+                        reg = <0x80000000 0x60000000>,
+                                <0xf9000000 0x00100000>;
+                        reg-names = "axi_h2f", "axi_h2f_lw";
+                        //clocks = <&iopll_0 1 &clk_0 &dp_0_video_pll 3 &iopll_0 0>;
+                        //clock-names = "h2f_axi_clock", "h2f_lw_axi_clock", "f2sdram0_clock", "f2sdram2_clock";
+                        #address-cells = <2>;
+                        #size-cells = <1>;
+                        ranges = <0x00000000 0x00000000 0x80000000 0x00040000>,
+                                <0x00000001 0x00000000 0xf9003000 0x00000040>,
+                                <0x00000001 0x00000040 0xf9003040 0x00000008>;
+
+                        sgmii_1_gmii2sgmii: phy@100000000 {
+                                compatible = "altr,gmii-to-sgmii-2.0";
+                                reg = <0x00000001 0x00000000 0x00000040>,
+                                        <0x00000001 0x00000040 0x00000008>;
+                                reg-names = "eth_tse_control_port", "gmii_to_sgmii_adapter_avalon_slave";
+                                clocks = <&sgmii_1_clk_0 &gmac1 1 &sgmii_1_clk_125 &sgmii_1_clk_125>;
+                                clock-names = "clock_in", "emac_gtx_clk", "tse_pcs_ref_clk_clock_connection", "tse_rx_cdr_refclk";
+                        }; //end phy@0x100000040 (sgmii_1_gmii2sgmii)
+                };
+	};
+};
+
+&gmac1 {
+        altr,gmii-to-sgmii-converter = <&sgmii_1_gmii2sgmii>;
+        altr,gmii_to_sgmii_converter = <&sgmii_1_gmii2sgmii>;
+        phy-mode = "sgmii";
+        status = "okay";
+};
+
+
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
index cb3147e23c5f..473b3328d63a 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
@@ -3,6 +3,7 @@
  * Copyright (C) 2019, Intel Corporation
  */
 #include "socfpga_agilex.dtsi"
+#include "socfpga_agilex_ghrd_sgmii.dtsi"
 
 / {
 	model = "SoCFPGA Agilex SoCDK";
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts
index 979aa59a6bd0..3341baed9bee 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts
@@ -3,6 +3,7 @@
  * Copyright (C) 2019, Intel Corporation
  */
 #include "socfpga_agilex.dtsi"
+#include "socfpga_agilex_ghrd_sgmii.dtsi"
 
 / {
 	model = "SoCFPGA Agilex SoCDK";
-- 
2.17.1

