coreclk_out
2019.06.24.10:00:08
Datasheet
Overview
Memory Map
altera_clock_bridge_inst
altera_clock_bridge v19.1
Parameters
DERIVED_CLOCK_RATE
250000000
EXPLICIT_CLOCK_RATE
250000000
NUM_CLOCK_OUTPUTS
1
deviceFamily
UNKNOWN
generateLegacySim
false
Software Assignments
(none)
generation took 0.00 seconds
rendering took 0.01 seconds