s10_hps

2019.06.28.18:30:46 Datasheet
Overview

Memory Map
altera_stratix10_hps_inst_arm_a9_0 altera_stratix10_hps_inst_arm_a9_1
 altera_axi_master  altera_axi_master

altera_stratix10_hps_inst

altera_stratix10_hps v19.1


Parameters

MPU_EVENTS_Enable false
GP_Enable false
DEBUG_APB_Enable false
STM_Enable true
CTI_Enable false
DDR_ATB_Enable false
F2S_mode 0
F2S_Width 3
F2S_ready_latency 0
F2S_ADDRESS_WIDTH 32
S2F_Width 3
S2F_ready_latency 0
S2F_ADDRESS_WIDTH 32
LWH2F_Enable 1
LWH2F_ready_latency 0
LWH2F_ADDRESS_WIDTH 21
F2SDRAM0_Width 3
F2SDRAM0_ready_latency 0
F2SDRAM1_Width 3
F2SDRAM1_ready_latency 0
F2SDRAM2_Width 3
F2SDRAM2_ready_latency 0
F2SDRAM_ADDRESS_WIDTH 32
HPS_BOOT 1
DMA_PeriphId_DERIVED 0,1,2,3,4,5,6,7
DMA_Enable No,No,No,No,No,No,No,No
F2SINTERRUPT_Enable true
S2FINTERRUPT_CLOCKPERIPHERAL_Enable false
S2FINTERRUPT_DMA_Enable false
S2FINTERRUPT_EMAC0_Enable false
S2FINTERRUPT_EMAC1_Enable false
S2FINTERRUPT_EMAC2_Enable false
S2FINTERRUPT_GPIO_Enable false
S2FINTERRUPT_I2CEMAC0_Enable false
S2FINTERRUPT_I2CEMAC1_Enable false
S2FINTERRUPT_I2CEMAC2_Enable false
S2FINTERRUPT_I2C0_Enable false
S2FINTERRUPT_I2C1_Enable false
S2FINTERRUPT_L4TIMER_Enable false
S2FINTERRUPT_NAND_Enable false
S2FINTERRUPT_SYSTIMER_Enable false
S2FINTERRUPT_SDMMC_Enable false
S2FINTERRUPT_SPIM0_Enable false
S2FINTERRUPT_SPIM1_Enable false
S2FINTERRUPT_SPIS0_Enable false
S2FINTERRUPT_SPIS1_Enable false
S2FINTERRUPT_SYSTEMMANAGER_Enable false
S2FINTERRUPT_UART0_Enable false
S2FINTERRUPT_UART1_Enable false
S2FINTERRUPT_USB0_Enable false
S2FINTERRUPT_USB1_Enable false
S2FINTERRUPT_WATCHDOG_Enable false
eosc1_clk_mhz 25.0
F2H_FREE_CLK_Enable false
F2H_FREE_CLK_FREQ 200
FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_MD_CLK 2.5
FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_GTX_CLK 100
FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_MD_CLK 2.5
FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_GTX_CLK 125
FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC2_MD_CLK 2.5
FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC2_GTX_CLK 125
FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SDMMC_CCLK 100
FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM0_SCLK_OUT 100
FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM1_SCLK_OUT 100
FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C0_CLK 100
FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C1_CLK 100
FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2CEMAC0_CLK 100
FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2CEMAC1_CLK 100
FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2CEMAC2_CLK 100
DEFAULT_MPU_CLK 1000
MPU_CLK_VCCL 2
USE_DEFAULT_MPU_CLK false
CUSTOM_MPU_CLK 800
H2F_USER0_CLK_Enable false
H2F_USER0_CLK_FREQ 500
H2F_USER1_CLK_Enable false
H2F_USER1_CLK_FREQ 500
L3_MAIN_FREE_CLK 400
L4_SYS_FREE_CLK 1
NOCDIV_L4MAINCLK 0
NOCDIV_L4MPCLK 1
NOCDIV_L4SPCLK 2
NOCDIV_CS_ATCLK 0
NOCDIV_CS_PDBGCLK 1
NOCDIV_CS_TRACECLK 0
HPS_DIV_GPIO_FREQ2 200
EMAC0_CLK 250
EMAC1_CLK 250
EMAC2_CLK 250
CLK_MAIN_PLL_SOURCE2 0
CLK_PERI_PLL_SOURCE2 0
CLK_S2F_USER0_SOURCE 1
CLK_S2F_USER1_SOURCE 1
CLK_PSI_SOURCE 1
CLK_EMAC_PTP_SOURCE 1
CLK_GPIO_SOURCE 0
CLK_SDMMC_SOURCE 0
CLK_EMACA_SOURCE 1
CLK_EMACB_SOURCE 1
H2F_PENDING_RST_Enable false
H2F_COLD_RST_Enable false
watchdog_reset true
W_RESET_ACTION 0
EMIF_CONDUIT_Enable true
IO_INPUT_DELAY0 0
IO_OUTPUT_DELAY0 0
IO_INPUT_DELAY1 0
IO_OUTPUT_DELAY1 0
IO_INPUT_DELAY2 0
IO_OUTPUT_DELAY2 0
IO_INPUT_DELAY3 0
IO_OUTPUT_DELAY3 0
IO_INPUT_DELAY4 0
IO_OUTPUT_DELAY4 0
IO_INPUT_DELAY5 0
IO_OUTPUT_DELAY5 0
IO_INPUT_DELAY6 0
IO_OUTPUT_DELAY6 0
IO_INPUT_DELAY7 0
IO_OUTPUT_DELAY7 0
IO_INPUT_DELAY8 0
IO_OUTPUT_DELAY8 0
IO_INPUT_DELAY9 0
IO_OUTPUT_DELAY9 0
IO_INPUT_DELAY10 0
IO_OUTPUT_DELAY10 0
IO_INPUT_DELAY11 0
IO_OUTPUT_DELAY11 0
IO_INPUT_DELAY12 0
IO_OUTPUT_DELAY12 17
IO_INPUT_DELAY13 0
IO_OUTPUT_DELAY13 0
IO_INPUT_DELAY14 0
IO_OUTPUT_DELAY14 0
IO_INPUT_DELAY15 0
IO_OUTPUT_DELAY15 0
IO_INPUT_DELAY16 0
IO_OUTPUT_DELAY16 0
IO_INPUT_DELAY17 0
IO_OUTPUT_DELAY17 0
IO_INPUT_DELAY18 0
IO_OUTPUT_DELAY18 0
IO_INPUT_DELAY19 0
IO_OUTPUT_DELAY19 0
IO_INPUT_DELAY20 0
IO_OUTPUT_DELAY20 0
IO_INPUT_DELAY21 0
IO_OUTPUT_DELAY21 0
IO_INPUT_DELAY22 0
IO_OUTPUT_DELAY22 0
IO_INPUT_DELAY23 0
IO_OUTPUT_DELAY23 0
IO_INPUT_DELAY24 0
IO_OUTPUT_DELAY24 0
IO_INPUT_DELAY25 0
IO_OUTPUT_DELAY25 0
IO_INPUT_DELAY26 0
IO_OUTPUT_DELAY26 0
IO_INPUT_DELAY27 0
IO_OUTPUT_DELAY27 0
IO_INPUT_DELAY28 0
IO_OUTPUT_DELAY28 0
IO_INPUT_DELAY29 0
IO_OUTPUT_DELAY29 0
IO_INPUT_DELAY30 0
IO_OUTPUT_DELAY30 0
IO_INPUT_DELAY31 0
IO_OUTPUT_DELAY31 0
IO_INPUT_DELAY32 0
IO_OUTPUT_DELAY32 0
IO_INPUT_DELAY33 0
IO_OUTPUT_DELAY33 0
IO_INPUT_DELAY34 0
IO_OUTPUT_DELAY34 0
IO_INPUT_DELAY35 0
IO_OUTPUT_DELAY35 0
IO_INPUT_DELAY36 0
IO_OUTPUT_DELAY36 0
IO_INPUT_DELAY37 0
IO_OUTPUT_DELAY37 0
IO_INPUT_DELAY38 0
IO_OUTPUT_DELAY38 0
IO_INPUT_DELAY39 0
IO_OUTPUT_DELAY39 0
IO_INPUT_DELAY40 0
IO_OUTPUT_DELAY40 0
IO_INPUT_DELAY41 0
IO_OUTPUT_DELAY41 0
IO_INPUT_DELAY42 0
IO_OUTPUT_DELAY42 0
IO_INPUT_DELAY43 0
IO_OUTPUT_DELAY43 0
IO_INPUT_DELAY44 0
IO_OUTPUT_DELAY44 0
IO_INPUT_DELAY45 0
IO_OUTPUT_DELAY45 0
IO_INPUT_DELAY46 0
IO_OUTPUT_DELAY46 0
IO_INPUT_DELAY47 0
IO_OUTPUT_DELAY47 0
EMAC0_PTP false
EMAC1_PTP false
EMAC2_PTP false
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

altera_stratix10_hps_inst_fpga_interfaces

altera_stratix10_interface_generator v19.1


Parameters

interfaceDefinition constraints {{create_clock -name hps_emac1_gtx_clk -period 8.0 [ get_keepers { *~emac1_gmii_txclk.reg } ]} {create_clock -name hps_emac2_gtx_clk -period 8.0 [ get_keepers { *~emac2_gmii_txclk.reg } ]} {create_clock -name hps_emac_ptp_ref_clk -period 10 [get_ports {emac_ptp_ref_clock_clk}]} {set_false_path -to [get_registers {*gmii_rxclk.reg__nff *_rxclk_i.reg__nff}]}} instances {clocks_resets {signal_widths {f2s_free_clk 1 f2s_pending_rst_ack 1} parameters {} location HPSINTERFACECLOCKSRESETS_X87_Y397_N20 entity_name fourteennm_hps_interface_clocks_resets signal_default_terminations {f2s_free_clk 1 f2s_pending_rst_ack 1} signal_terminations {f2s_free_clk {0:0 0} f2s_pending_rst_ack {0:0 1}}} emif_interface {signal_widths {} parameters {} location {} entity_name one_hps_interface_ddr signal_default_terminations {} signal_terminations {}} stm_event {signal_widths {} parameters {} location HPSINTERFACESTMEVENT_X87_Y397_N34 entity_name fourteennm_hps_interface_stm_event signal_default_terminations {} signal_terminations {}} debug_apb {signal_widths {F2S_PCLKENDBG 1 F2S_DBGAPBDISABLE 1} parameters {} location HPSINTERFACEDBGAPB_X87_Y397_N30 entity_name fourteennm_hps_interface_dbg_apb signal_default_terminations {F2S_PCLKENDBG 0 F2S_DBGAPBDISABLE 0} signal_terminations {F2S_PCLKENDBG {0:0 0} F2S_DBGAPBDISABLE {0:0 0}}} @orderednames {clocks_resets debug_apb stm_event emif_interface f2h_interrupts peripheral_emac1 peripheral_emac2} peripheral_emac1 {signal_widths {} parameters {} location HPSINTERFACEPERIPHERALEMAC_X87_Y397_N15 entity_name fourteennm_hps_interface_peripheral_emac signal_default_terminations {} signal_terminations {}} peripheral_emac2 {signal_widths {} parameters {} location HPSINTERFACEPERIPHERALEMAC_X87_Y397_N16 entity_name fourteennm_hps_interface_peripheral_emac signal_default_terminations {} signal_terminations {}} f2h_interrupts {signal_widths {} parameters {} location HPSMPFEINTERRUPTS_X53_Y325_N2 entity_name fourteennm_hps_mpfe_interrupts signal_default_terminations {} signal_terminations {}}} interfaces {@orderednames {h2f_reset h2f_watchdog_rst f2h_stm_hw_events hps_emif emac_ptp_ref_clock emac1 emac1_md_clk emac1_rx_clk_in emac1_tx_clk_in emac1_gtx_clk emac1_tx_reset emac1_rx_reset emac2 emac2_md_clk emac2_rx_clk_in emac2_tx_clk_in emac2_gtx_clk emac2_tx_reset emac2_rx_reset} h2f_reset {properties {associatedResetSinks none synchronousEdges none} direction Output type reset signals {@orderednames h2f_rst h2f_rst {width 1 properties {} instance_name clocks_resets internal_name s2f_rst direction Output role reset fragments {}}}} h2f_watchdog_rst {properties {associatedResetSinks none synchronousEdges none} direction Output type reset signals {@orderednames h2f_watchdog_rst h2f_watchdog_rst {width 1 properties {} instance_name clocks_resets internal_name s2f_watchdog_rst direction Output role reset_n fragments {}}}} f2h_stm_hw_events {properties {} direction Input type conduit signals {@orderednames f2h_stm_hwevents f2h_stm_hwevents {width 43 properties {} instance_name stm_event internal_name f2s_stm_event direction Input role stm_hwevents fragments {}}}} hps_emif {properties {} direction Output type conduit signals {@orderednames {hps_emif_emif_to_hps hps_emif_hps_to_emif hps_emif_emif_to_gp hps_emif_gp_to_emif} hps_emif_emif_to_hps {width 4096 properties {} instance_name emif_interface internal_name io48_b_cdata_pb0_in direction Input role emif_to_hps fragments {}} hps_emif_hps_to_emif {width 4096 properties {} instance_name emif_interface internal_name io48_b_iod_pb0_out direction Output role hps_to_emif fragments {}} hps_emif_emif_to_gp {width 1 properties {} instance_name hps_emif internal_name hps_emif_emif_to_gp direction Input role emif_to_gp fragments {}} hps_emif_gp_to_emif {width 2 properties {} instance_name hps_emif internal_name hps_emif_gp_to_emif direction Output role gp_to_emif fragments {}}}} emac_ptp_ref_clock {properties {} direction Input type clock signals {@orderednames emac_ptp_ref_clk emac_ptp_ref_clk {width 1 properties {} instance_name clocks_resets internal_name emac_ptp_ref_clk direction Input role clk fragments {}}}} emac1 {properties {} direction Input no_export 0 type conduit signals {@orderednames {emac1_phy_mac_speed_o emac1_phy_txd_o emac1_phy_txen_o emac1_phy_txer_o emac1_phy_rxdv_i emac1_phy_rxer_i emac1_phy_rxd_i emac1_phy_col_i emac1_phy_crs_i emac1_gmii_mdo_o emac1_gmii_mdo_o_e emac1_gmii_mdi_i emac1_ptp_pps_o emac1_ptp_aux_ts_trig_i emac1_ptp_tstmp_data emac1_ptp_tstmp_en} emac1_phy_mac_speed_o {width 2 properties {} instance_name peripheral_emac1 internal_name phy_mac_speed_o direction Output role phy_mac_speed_o fragments {}} emac1_phy_txd_o {width 8 properties {} instance_name peripheral_emac1 internal_name phy_txd_o direction Output role phy_txd_o fragments {}} emac1_phy_txen_o {width 1 properties {} instance_name peripheral_emac1 internal_name phy_txen_o direction Output role phy_txen_o fragments {}} emac1_phy_txer_o {width 1 properties {} instance_name peripheral_emac1 internal_name phy_txer_o direction Output role phy_txer_o fragments {}} emac1_phy_rxdv_i {width 1 properties {} instance_name peripheral_emac1 internal_name phy_rxdv_i direction Input role phy_rxdv_i fragments {}} emac1_phy_rxer_i {width 1 properties {} instance_name peripheral_emac1 internal_name phy_rxer_i direction Input role phy_rxer_i fragments {}} emac1_phy_rxd_i {width 8 properties {} instance_name peripheral_emac1 internal_name phy_rxd_i direction Input role phy_rxd_i fragments {}} emac1_phy_col_i {width 1 properties {} instance_name peripheral_emac1 internal_name phy_col_i direction Input role phy_col_i fragments {}} emac1_phy_crs_i {width 1 properties {} instance_name peripheral_emac1 internal_name phy_crs_i direction Input role phy_crs_i fragments {}} emac1_gmii_mdo_o {width 1 properties {} instance_name peripheral_emac1 internal_name gmii_mdo_o direction Output role gmii_mdo_o fragments {}} emac1_gmii_mdo_o_e {width 1 properties {} instance_name peripheral_emac1 internal_name gmii_mdo_o_e direction Output role gmii_mdo_o_e fragments {}} emac1_gmii_mdi_i {width 1 properties {} instance_name peripheral_emac1 internal_name gmii_mdi_i direction Input role gmii_mdi_i fragments {}} emac1_ptp_pps_o {width 1 properties {} instance_name peripheral_emac1 internal_name ptp_pps_o direction Output role ptp_pps_o fragments {}} emac1_ptp_aux_ts_trig_i {width 1 properties {} instance_name peripheral_emac1 internal_name ptp_aux_ts_trig_i direction Input role ptp_aux_ts_trig_i fragments {}} emac1_ptp_tstmp_data {width 1 properties {} instance_name peripheral_emac1 internal_name ptp_tstmp_data direction Output role ptp_tstmp_data fragments {}} emac1_ptp_tstmp_en {width 1 properties {} instance_name peripheral_emac1 internal_name ptp_tstmp_en direction Output role ptp_tstmp_en fragments {}}}} emac1_md_clk {properties {clockRate 2500000.0 clockRateKnown true} direction Output no_export 0 type clock signals {@orderednames emac1_gmii_mdc_o emac1_gmii_mdc_o {width 1 properties {} instance_name peripheral_emac1 internal_name gmii_mdc_o direction Output role clk fragments {}}}} emac1_rx_clk_in {properties {} direction Input no_export 0 type clock signals {@orderednames emac1_clk_rx_i emac1_clk_rx_i {width 1 properties {} instance_name peripheral_emac1 internal_name phy_rxclk_i direction Input role clk fragments {}}}} emac1_tx_clk_in {properties {} direction Input no_export 0 type clock signals {@orderednames emac1_clk_tx_i emac1_clk_tx_i {width 1 properties {} instance_name peripheral_emac1 internal_name phy_txclk_i direction Input role clk fragments {}}}} emac1_gtx_clk {properties {clockRate 125000000.0 clockRateKnown true} direction Output no_export 0 type clock signals {@orderednames emac1_phy_txclk_o emac1_phy_txclk_o {width 1 properties {} instance_name peripheral_emac1 internal_name phy_txclk_o_hio direction Output role clk fragments {}}}} emac1_tx_reset {properties {associatedClock emac1_tx_clk_in associatedResetSinks none} direction Output no_export 0 type reset signals {@orderednames emac1_rst_clk_tx_n_o emac1_rst_clk_tx_n_o {width 1 properties {} instance_name peripheral_emac1 internal_name rst_clk_tx_n_o direction Output role reset_n fragments {}}}} emac1_rx_reset {properties {associatedClock emac1_rx_clk_in associatedResetSinks none} direction Output no_export 0 type reset signals {@orderednames emac1_rst_clk_rx_n_o emac1_rst_clk_rx_n_o {width 1 properties {} instance_name peripheral_emac1 internal_name rst_clk_rx_n_o direction Output role reset_n fragments {}}}} emac2 {properties {} direction Input no_export 0 type conduit signals {@orderednames {emac2_phy_mac_speed_o emac2_phy_txd_o emac2_phy_txen_o emac2_phy_txer_o emac2_phy_rxdv_i emac2_phy_rxer_i emac2_phy_rxd_i emac2_phy_col_i emac2_phy_crs_i emac2_gmii_mdo_o emac2_gmii_mdo_o_e emac2_gmii_mdi_i emac2_ptp_pps_o emac2_ptp_aux_ts_trig_i emac2_ptp_tstmp_data emac2_ptp_tstmp_en} emac2_phy_mac_speed_o {width 2 properties {} instance_name peripheral_emac2 internal_name phy_mac_speed_o direction Output role phy_mac_speed_o fragments {}} emac2_phy_txd_o {width 8 properties {} instance_name peripheral_emac2 internal_name phy_txd_o direction Output role phy_txd_o fragments {}} emac2_phy_txen_o {width 1 properties {} instance_name peripheral_emac2 internal_name phy_txen_o direction Output role phy_txen_o fragments {}} emac2_phy_txer_o {width 1 properties {} instance_name peripheral_emac2 internal_name phy_txer_o direction Output role phy_txer_o fragments {}} emac2_phy_rxdv_i {width 1 properties {} instance_name peripheral_emac2 internal_name phy_rxdv_i direction Input role phy_rxdv_i fragments {}} emac2_phy_rxer_i {width 1 properties {} instance_name peripheral_emac2 internal_name phy_rxer_i direction Input role phy_rxer_i fragments {}} emac2_phy_rxd_i {width 8 properties {} instance_name peripheral_emac2 internal_name phy_rxd_i direction Input role phy_rxd_i fragments {}} emac2_phy_col_i {width 1 properties {} instance_name peripheral_emac2 internal_name phy_col_i direction Input role phy_col_i fragments {}} emac2_phy_crs_i {width 1 properties {} instance_name peripheral_emac2 internal_name phy_crs_i direction Input role phy_crs_i fragments {}} emac2_gmii_mdo_o {width 1 properties {} instance_name peripheral_emac2 internal_name gmii_mdo_o direction Output role gmii_mdo_o fragments {}} emac2_gmii_mdo_o_e {width 1 properties {} instance_name peripheral_emac2 internal_name gmii_mdo_o_e direction Output role gmii_mdo_o_e fragments {}} emac2_gmii_mdi_i {width 1 properties {} instance_name peripheral_emac2 internal_name gmii_mdi_i direction Input role gmii_mdi_i fragments {}} emac2_ptp_pps_o {width 1 properties {} instance_name peripheral_emac2 internal_name ptp_pps_o direction Output role ptp_pps_o fragments {}} emac2_ptp_aux_ts_trig_i {width 1 properties {} instance_name peripheral_emac2 internal_name ptp_aux_ts_trig_i direction Input role ptp_aux_ts_trig_i fragments {}} emac2_ptp_tstmp_data {width 1 properties {} instance_name peripheral_emac2 internal_name ptp_tstmp_data direction Output role ptp_tstmp_data fragments {}} emac2_ptp_tstmp_en {width 1 properties {} instance_name peripheral_emac2 internal_name ptp_tstmp_en direction Output role ptp_tstmp_en fragments {}}}} emac2_md_clk {properties {clockRate 2500000.0 clockRateKnown true} direction Output no_export 0 type clock signals {@orderednames emac2_gmii_mdc_o emac2_gmii_mdc_o {width 1 properties {} instance_name peripheral_emac2 internal_name gmii_mdc_o direction Output role clk fragments {}}}} emac2_rx_clk_in {properties {} direction Input no_export 0 type clock signals {@orderednames emac2_clk_rx_i emac2_clk_rx_i {width 1 properties {} instance_name peripheral_emac2 internal_name phy_rxclk_i direction Input role clk fragments {}}}} emac2_tx_clk_in {properties {} direction Input no_export 0 type clock signals {@orderednames emac2_clk_tx_i emac2_clk_tx_i {width 1 properties {} instance_name peripheral_emac2 internal_name phy_txclk_i direction Input role clk fragments {}}}} emac2_gtx_clk {properties {clockRate 125000000.0 clockRateKnown true} direction Output no_export 0 type clock signals {@orderednames emac2_phy_txclk_o emac2_phy_txclk_o {width 1 properties {} instance_name peripheral_emac2 internal_name phy_txclk_o_hio direction Output role clk fragments {}}}} emac2_tx_reset {properties {associatedClock emac2_tx_clk_in associatedResetSinks none} direction Output no_export 0 type reset signals {@orderednames emac2_rst_clk_tx_n_o emac2_rst_clk_tx_n_o {width 1 properties {} instance_name peripheral_emac2 internal_name rst_clk_tx_n_o direction Output role reset_n fragments {}}}} emac2_rx_reset {properties {associatedClock emac2_rx_clk_in associatedResetSinks none} direction Output no_export 0 type reset signals {@orderednames emac2_rst_clk_rx_n_o emac2_rst_clk_rx_n_o {width 1 properties {} instance_name peripheral_emac2 internal_name rst_clk_rx_n_o direction Output role reset_n fragments {}}}}} properties {} interface_sim_style {} raw_assigns {} intermediate_wire_count 0 raw_assign_sim_style {} wires_to_fragments {} wire_sim_style {}
qipEntries
ignoreSimulation false
hps_parameter_map
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

altera_stratix10_hps_inst_hps_io

altera_stratix10_hps_io v19.1


Parameters

border_description constraints {} instances {phery_usb0 {signal_widths {} parameters {} location HPSPERIPHERALUSB_X87_Y398_N18 entity_name fourteennm_hps_peripheral_usb signal_default_terminations {} signal_terminations {}} phery_emac0 {signal_widths {} parameters {} location HPSPERIPHERALEMAC_X87_Y398_N0 entity_name fourteennm_hps_peripheral_emac signal_default_terminations {} signal_terminations {}} @orderednames {phery_emac0 phery_sdmmc phery_usb0 phery_uart0 phery_i2c1 gpio} phery_i2c1 {signal_widths {} parameters {} location HPSPERIPHERALI2C_X87_Y398_N5 entity_name fourteennm_hps_peripheral_i2c signal_default_terminations {} signal_terminations {}} gpio {signal_widths {} parameters {} location HPSPERIPHERALGPIO_X87_Y398_N3 entity_name fourteennm_hps_peripheral_gpio signal_default_terminations {} signal_terminations {}} phery_uart0 {signal_widths {} parameters {} location HPSPERIPHERALUART_X87_Y398_N16 entity_name fourteennm_hps_peripheral_uart signal_default_terminations {} signal_terminations {}} phery_sdmmc {signal_widths {} parameters {} location HPSPERIPHERALSDMMC_X87_Y398_N11 entity_name fourteennm_hps_peripheral_sdmmc signal_default_terminations {} signal_terminations {}}} interfaces {@orderednames hps_io hps_io {properties {} direction input type conduit signals {@orderednames {hps_io_phery_emac0_TX_CLK hps_io_phery_emac0_TXD0 hps_io_phery_emac0_TXD1 hps_io_phery_emac0_TXD2 hps_io_phery_emac0_TXD3 hps_io_phery_emac0_RX_CTL hps_io_phery_emac0_TX_CTL hps_io_phery_emac0_RX_CLK hps_io_phery_emac0_RXD0 hps_io_phery_emac0_RXD1 hps_io_phery_emac0_RXD2 hps_io_phery_emac0_RXD3 hps_io_phery_emac0_MDIO hps_io_phery_emac0_MDC hps_io_phery_sdmmc_CMD hps_io_phery_sdmmc_D0 hps_io_phery_sdmmc_D1 hps_io_phery_sdmmc_D2 hps_io_phery_sdmmc_D3 hps_io_phery_sdmmc_CCLK hps_io_phery_usb0_DATA0 hps_io_phery_usb0_DATA1 hps_io_phery_usb0_DATA2 hps_io_phery_usb0_DATA3 hps_io_phery_usb0_DATA4 hps_io_phery_usb0_DATA5 hps_io_phery_usb0_DATA6 hps_io_phery_usb0_DATA7 hps_io_phery_usb0_CLK hps_io_phery_usb0_STP hps_io_phery_usb0_DIR hps_io_phery_usb0_NXT hps_io_phery_uart0_RX hps_io_phery_uart0_TX hps_io_phery_i2c1_SDA hps_io_phery_i2c1_SCL hps_io_gpio_gpio1_io0 hps_io_gpio_gpio1_io1 hps_io_gpio_gpio1_io4 hps_io_gpio_gpio1_io5 hps_io_jtag_tck hps_io_jtag_tms hps_io_jtag_tdo hps_io_jtag_tdi hps_io_hps_ocs_clk hps_io_gpio_gpio1_io19 hps_io_gpio_gpio1_io20 hps_io_gpio_gpio1_io21} hps_io_phery_emac0_TX_CLK {width 1 properties {} instance_name hps_io internal_name hps_io_phery_emac0_TX_CLK direction output role hps_io_phery_emac0_TX_CLK fragments phery_emac0:EMAC_CLK_TX(0:0)} hps_io_phery_emac0_TXD0 {width 1 properties {} instance_name hps_io internal_name hps_io_phery_emac0_TXD0 direction output role hps_io_phery_emac0_TXD0 fragments phery_emac0:EMAC_PHY_TXD(0:0)} hps_io_phery_emac0_TXD1 {width 1 properties {} instance_name hps_io internal_name hps_io_phery_emac0_TXD1 direction output role hps_io_phery_emac0_TXD1 fragments phery_emac0:EMAC_PHY_TXD(1:1)} hps_io_phery_emac0_TXD2 {width 1 properties {} instance_name hps_io internal_name hps_io_phery_emac0_TXD2 direction output role hps_io_phery_emac0_TXD2 fragments phery_emac0:EMAC_PHY_TXD(2:2)} hps_io_phery_emac0_TXD3 {width 1 properties {} instance_name hps_io internal_name hps_io_phery_emac0_TXD3 direction output role hps_io_phery_emac0_TXD3 fragments phery_emac0:EMAC_PHY_TXD(3:3)} hps_io_phery_emac0_RX_CTL {width 1 properties {} instance_name hps_io internal_name hps_io_phery_emac0_RX_CTL direction input role hps_io_phery_emac0_RX_CTL fragments phery_emac0:EMAC_PHY_RXDV(0:0)} hps_io_phery_emac0_TX_CTL {width 1 properties {} instance_name hps_io internal_name hps_io_phery_emac0_TX_CTL direction output role hps_io_phery_emac0_TX_CTL fragments phery_emac0:EMAC_PHY_TX_OE(0:0)} hps_io_phery_emac0_RX_CLK {width 1 properties {} instance_name hps_io internal_name hps_io_phery_emac0_RX_CLK direction input role hps_io_phery_emac0_RX_CLK fragments phery_emac0:EMAC_CLK_RX(0:0)} hps_io_phery_emac0_RXD0 {width 1 properties {} instance_name hps_io internal_name hps_io_phery_emac0_RXD0 direction input role hps_io_phery_emac0_RXD0 fragments phery_emac0:EMAC_PHY_RXD(0:0)} hps_io_phery_emac0_RXD1 {width 1 properties {} instance_name hps_io internal_name hps_io_phery_emac0_RXD1 direction input role hps_io_phery_emac0_RXD1 fragments phery_emac0:EMAC_PHY_RXD(1:1)} hps_io_phery_emac0_RXD2 {width 1 properties {} instance_name hps_io internal_name hps_io_phery_emac0_RXD2 direction input role hps_io_phery_emac0_RXD2 fragments phery_emac0:EMAC_PHY_RXD(2:2)} hps_io_phery_emac0_RXD3 {width 1 properties {} instance_name hps_io internal_name hps_io_phery_emac0_RXD3 direction input role hps_io_phery_emac0_RXD3 fragments phery_emac0:EMAC_PHY_RXD(3:3)} hps_io_phery_emac0_MDIO {tristate_output {{intermediate 1} {intermediate 0}} width 1 properties {} instance_name hps_io internal_name hps_io_phery_emac0_MDIO direction bidir role hps_io_phery_emac0_MDIO fragments phery_emac0:EMAC_GMII_MDO_I(0:0)} hps_io_phery_emac0_MDC {width 1 properties {} instance_name hps_io internal_name hps_io_phery_emac0_MDC direction output role hps_io_phery_emac0_MDC fragments phery_emac0:EMAC_GMII_MDC(0:0)} hps_io_phery_sdmmc_CMD {tristate_output {{intermediate 3} {intermediate 2}} width 1 properties {} instance_name hps_io internal_name hps_io_phery_sdmmc_CMD direction bidir role hps_io_phery_sdmmc_CMD fragments phery_sdmmc:SDMMC_CMD_I(0:0)} hps_io_phery_sdmmc_D0 {tristate_output {{intermediate 5} {intermediate 4}} width 1 properties {} instance_name hps_io internal_name hps_io_phery_sdmmc_D0 direction bidir role hps_io_phery_sdmmc_D0 fragments phery_sdmmc:SDMMC_DATA_I(0:0)} hps_io_phery_sdmmc_D1 {tristate_output {{intermediate 7} {intermediate 6}} width 1 properties {} instance_name hps_io internal_name hps_io_phery_sdmmc_D1 direction bidir role hps_io_phery_sdmmc_D1 fragments phery_sdmmc:SDMMC_DATA_I(1:1)} hps_io_phery_sdmmc_D2 {tristate_output {{intermediate 9} {intermediate 8}} width 1 properties {} instance_name hps_io internal_name hps_io_phery_sdmmc_D2 direction bidir role hps_io_phery_sdmmc_D2 fragments phery_sdmmc:SDMMC_DATA_I(2:2)} hps_io_phery_sdmmc_D3 {tristate_output {{intermediate 11} {intermediate 10}} width 1 properties {} instance_name hps_io internal_name hps_io_phery_sdmmc_D3 direction bidir role hps_io_phery_sdmmc_D3 fragments phery_sdmmc:SDMMC_DATA_I(3:3)} hps_io_phery_sdmmc_CCLK {width 1 properties {} instance_name hps_io internal_name hps_io_phery_sdmmc_CCLK direction output role hps_io_phery_sdmmc_CCLK fragments phery_sdmmc:SDMMC_CCLK(0:0)} hps_io_phery_usb0_DATA0 {tristate_output {{intermediate 13} {intermediate 12}} width 1 properties {} instance_name hps_io internal_name hps_io_phery_usb0_DATA0 direction bidir role hps_io_phery_usb0_DATA0 fragments phery_usb0:USB_ULPI_DATA_I(0:0)} hps_io_phery_usb0_DATA1 {tristate_output {{intermediate 15} {intermediate 14}} width 1 properties {} instance_name hps_io internal_name hps_io_phery_usb0_DATA1 direction bidir role hps_io_phery_usb0_DATA1 fragments phery_usb0:USB_ULPI_DATA_I(1:1)} hps_io_phery_usb0_DATA2 {tristate_output {{intermediate 17} {intermediate 16}} width 1 properties {} instance_name hps_io internal_name hps_io_phery_usb0_DATA2 direction bidir role hps_io_phery_usb0_DATA2 fragments phery_usb0:USB_ULPI_DATA_I(2:2)} hps_io_phery_usb0_DATA3 {tristate_output {{intermediate 19} {intermediate 18}} width 1 properties {} instance_name hps_io internal_name hps_io_phery_usb0_DATA3 direction bidir role hps_io_phery_usb0_DATA3 fragments phery_usb0:USB_ULPI_DATA_I(3:3)} hps_io_phery_usb0_DATA4 {tristate_output {{intermediate 21} {intermediate 20}} width 1 properties {} instance_name hps_io internal_name hps_io_phery_usb0_DATA4 direction bidir role hps_io_phery_usb0_DATA4 fragments phery_usb0:USB_ULPI_DATA_I(4:4)} hps_io_phery_usb0_DATA5 {tristate_output {{intermediate 23} {intermediate 22}} width 1 properties {} instance_name hps_io internal_name hps_io_phery_usb0_DATA5 direction bidir role hps_io_phery_usb0_DATA5 fragments phery_usb0:USB_ULPI_DATA_I(5:5)} hps_io_phery_usb0_DATA6 {tristate_output {{intermediate 25} {intermediate 24}} width 1 properties {} instance_name hps_io internal_name hps_io_phery_usb0_DATA6 direction bidir role hps_io_phery_usb0_DATA6 fragments phery_usb0:USB_ULPI_DATA_I(6:6)} hps_io_phery_usb0_DATA7 {tristate_output {{intermediate 27} {intermediate 26}} width 1 properties {} instance_name hps_io internal_name hps_io_phery_usb0_DATA7 direction bidir role hps_io_phery_usb0_DATA7 fragments phery_usb0:USB_ULPI_DATA_I(7:7)} hps_io_phery_usb0_CLK {width 1 properties {} instance_name hps_io internal_name hps_io_phery_usb0_CLK direction input role hps_io_phery_usb0_CLK fragments phery_usb0:USB_ULPI_CLK(0:0)} hps_io_phery_usb0_STP {width 1 properties {} instance_name hps_io internal_name hps_io_phery_usb0_STP direction output role hps_io_phery_usb0_STP fragments phery_usb0:USB_ULPI_STP(0:0)} hps_io_phery_usb0_DIR {width 1 properties {} instance_name hps_io internal_name hps_io_phery_usb0_DIR direction input role hps_io_phery_usb0_DIR fragments phery_usb0:USB_ULPI_DIR(0:0)} hps_io_phery_usb0_NXT {width 1 properties {} instance_name hps_io internal_name hps_io_phery_usb0_NXT direction input role hps_io_phery_usb0_NXT fragments phery_usb0:USB_ULPI_NXT(0:0)} hps_io_phery_uart0_RX {width 1 properties {} instance_name hps_io internal_name hps_io_phery_uart0_RX direction input role hps_io_phery_uart0_RX fragments phery_uart0:UART_RXD(0:0)} hps_io_phery_uart0_TX {width 1 properties {} instance_name hps_io internal_name hps_io_phery_uart0_TX direction output role hps_io_phery_uart0_TX fragments phery_uart0:UART_TXD(0:0)} hps_io_phery_i2c1_SDA {tristate_output {{intermediate 28} {}} width 1 properties {} instance_name hps_io internal_name hps_io_phery_i2c1_SDA direction bidir role hps_io_phery_i2c1_SDA fragments phery_i2c1:I2C_DATA(0:0)} hps_io_phery_i2c1_SCL {tristate_output {{intermediate 29} {}} width 1 properties {} instance_name hps_io internal_name hps_io_phery_i2c1_SCL direction bidir role hps_io_phery_i2c1_SCL fragments phery_i2c1:I2C_CLK(0:0)} hps_io_gpio_gpio1_io0 {tristate_output {{intermediate 31} {intermediate 30}} width 1 properties {} instance_name hps_io internal_name hps_io_gpio_gpio1_io0 direction bidir role hps_io_gpio_gpio1_io0 fragments gpio:GPIO1_PORTA_I(0:0)} hps_io_gpio_gpio1_io1 {tristate_output {{intermediate 33} {intermediate 32}} width 1 properties {} instance_name hps_io internal_name hps_io_gpio_gpio1_io1 direction bidir role hps_io_gpio_gpio1_io1 fragments gpio:GPIO1_PORTA_I(1:1)} hps_io_gpio_gpio1_io4 {tristate_output {{intermediate 35} {intermediate 34}} width 1 properties {} instance_name hps_io internal_name hps_io_gpio_gpio1_io4 direction bidir role hps_io_gpio_gpio1_io4 fragments gpio:GPIO1_PORTA_I(4:4)} hps_io_gpio_gpio1_io5 {tristate_output {{intermediate 37} {intermediate 36}} width 1 properties {} instance_name hps_io internal_name hps_io_gpio_gpio1_io5 direction bidir role hps_io_gpio_gpio1_io5 fragments gpio:GPIO1_PORTA_I(5:5)} hps_io_jtag_tck {width 1 properties {} instance_name hps_io internal_name hps_io_jtag_tck direction input role hps_io_jtag_tck fragments gpio:GPIO1_PORTA_I(8:8)} hps_io_jtag_tms {width 1 properties {} instance_name hps_io internal_name hps_io_jtag_tms direction input role hps_io_jtag_tms fragments gpio:GPIO1_PORTA_I(9:9)} hps_io_jtag_tdo {width 1 properties {} instance_name hps_io internal_name hps_io_jtag_tdo direction output role hps_io_jtag_tdo fragments gpio:GPIO1_PORTA_O(10:10)} hps_io_jtag_tdi {width 1 properties {} instance_name hps_io internal_name hps_io_jtag_tdi direction input role hps_io_jtag_tdi fragments gpio:GPIO1_PORTA_I(11:11)} hps_io_hps_ocs_clk {width 1 properties {} instance_name hps_io internal_name hps_io_hps_ocs_clk direction input role hps_io_hps_ocs_clk fragments gpio:GPIO1_PORTA_I(18:18)} hps_io_gpio_gpio1_io19 {tristate_output {{intermediate 39} {intermediate 38}} width 1 properties {} instance_name hps_io internal_name hps_io_gpio_gpio1_io19 direction bidir role hps_io_gpio_gpio1_io19 fragments gpio:GPIO1_PORTA_I(19:19)} hps_io_gpio_gpio1_io20 {tristate_output {{intermediate 41} {intermediate 40}} width 1 properties {} instance_name hps_io internal_name hps_io_gpio_gpio1_io20 direction bidir role hps_io_gpio_gpio1_io20 fragments gpio:GPIO1_PORTA_I(20:20)} hps_io_gpio_gpio1_io21 {tristate_output {{intermediate 43} {intermediate 42}} width 1 properties {} instance_name hps_io internal_name hps_io_gpio_gpio1_io21 direction bidir role hps_io_gpio_gpio1_io21 fragments gpio:GPIO1_PORTA_I(21:21)}}}} properties {GENERATE_ISW 1} interface_sim_style {} raw_assigns {} intermediate_wire_count 44 raw_assign_sim_style {} wires_to_fragments {{intermediate 41} {output gpio:GPIO1_PORTA_OE(20:20)} {intermediate 23} {output phery_usb0:USB_ULPI_DATA_OE(5:5)} {intermediate 42} {output gpio:GPIO1_PORTA_O(21:21)} {intermediate 24} {output phery_usb0:USB_ULPI_DATA_O(6:6)} {intermediate 43} {output gpio:GPIO1_PORTA_OE(21:21)} {intermediate 25} {output phery_usb0:USB_ULPI_DATA_OE(6:6)} {intermediate 26} {output phery_usb0:USB_ULPI_DATA_O(7:7)} {intermediate 0} {output phery_emac0:EMAC_GMII_MDO_O(0:0)} {intermediate 27} {output phery_usb0:USB_ULPI_DATA_OE(7:7)} {intermediate 1} {output phery_emac0:EMAC_GMII_MDO_OE(0:0)} {intermediate 10} {output phery_sdmmc:SDMMC_DATA_O(3:3)} {intermediate 28} {output phery_i2c1:I2C_DATA_OE(0:0)} {intermediate 2} {output phery_sdmmc:SDMMC_CMD_O(0:0)} {intermediate 11} {output phery_sdmmc:SDMMC_DATA_OE(3:3)} {intermediate 30} {output gpio:GPIO1_PORTA_O(0:0)} {intermediate 29} {output phery_i2c1:I2C_CLK_OE(0:0)} {intermediate 12} {output phery_usb0:USB_ULPI_DATA_O(0:0)} {intermediate 3} {output phery_sdmmc:SDMMC_CMD_OE(0:0)} {intermediate 31} {output gpio:GPIO1_PORTA_OE(0:0)} {intermediate 13} {output phery_usb0:USB_ULPI_DATA_OE(0:0)} {intermediate 4} {output phery_sdmmc:SDMMC_DATA_O(0:0)} {intermediate 32} {output gpio:GPIO1_PORTA_O(1:1)} {intermediate 14} {output phery_usb0:USB_ULPI_DATA_O(1:1)} {intermediate 5} {output phery_sdmmc:SDMMC_DATA_OE(0:0)} {intermediate 33} {output gpio:GPIO1_PORTA_OE(1:1)} {intermediate 15} {output phery_usb0:USB_ULPI_DATA_OE(1:1)} {intermediate 6} {output phery_sdmmc:SDMMC_DATA_O(1:1)} {intermediate 34} {output gpio:GPIO1_PORTA_O(4:4)} {intermediate 16} {output phery_usb0:USB_ULPI_DATA_O(2:2)} {intermediate 7} {output phery_sdmmc:SDMMC_DATA_OE(1:1)} {intermediate 35} {output gpio:GPIO1_PORTA_OE(4:4)} {intermediate 17} {output phery_usb0:USB_ULPI_DATA_OE(2:2)} {intermediate 8} {output phery_sdmmc:SDMMC_DATA_O(2:2)} {intermediate 36} {output gpio:GPIO1_PORTA_O(5:5)} {intermediate 18} {output phery_usb0:USB_ULPI_DATA_O(3:3)} {intermediate 9} {output phery_sdmmc:SDMMC_DATA_OE(2:2)} {intermediate 37} {output gpio:GPIO1_PORTA_OE(5:5)} {intermediate 20} {output phery_usb0:USB_ULPI_DATA_O(4:4)} {intermediate 19} {output phery_usb0:USB_ULPI_DATA_OE(3:3)} {intermediate 38} {output gpio:GPIO1_PORTA_O(19:19)} {intermediate 21} {output phery_usb0:USB_ULPI_DATA_OE(4:4)} {intermediate 40} {output gpio:GPIO1_PORTA_O(20:20)} {intermediate 39} {output gpio:GPIO1_PORTA_OE(19:19)} {intermediate 22} {output phery_usb0:USB_ULPI_DATA_O(5:5)}} wire_sim_style {}
hps_parameter_map H2F_DEBUG_APB_CLOCK_FREQ 100 quartus_ini_hps_ip_enable_jtag false MAINPLLGRP_NOC_CNT 5 SPIS1_Mode N/A MAINPLLGRP_SDMMC_CNT 1 test_iface_definition {DFT_IN_APS_TEST_SI 16 input DFT_IN_ATPG_CLK_SEL_N 1 input DFT_IN_ATPG_MODE_N 1 input DFT_IN_ATSPEED_DEFAULT_EN_N 1 input DFT_IN_ATSPEED_EN 1 input DFT_IN_BIST_EN_N 1 input DFT_IN_CLKOD_SCANCLK 1 input DFT_IN_CLKOD_SCANIN 1 input DFT_IN_COMPRESS_ENABLE_N 1 input DFT_IN_DFTMCPHOLD 1 input DFT_IN_DFTRAMHOLD 1 input DFT_IN_DFTRSTDISABLE 1 input DFT_IN_IO_CONFIG_N 32 input DFT_IN_IO_TEST_MODE_N 1 input DFT_IN_JTAG_HIGHZ_N 1 input DFT_IN_JTAG_MODE_N 1 input RST_DFX_OUT_DATA 23 output DFT_IN_MBIST_TCK 1 input DFT_IN_MBIST_TDI 1 input DFT_IN_MBIST_TMS 1 input DFT_IN_MBIST_TRST_N 1 input DFT_IN_MEM_DFTCLKEN 1 input DFT_IN_MEM_DFTMASK 1 input DFT_IN_MEMCONTROL_SHIFT_EN 1 input DFT_IN_MEMCONTROL_SHIFT_IN 1 input DFT_IN_MEMCONTROL_SHIFT_OUT 1 output DFT_IN_PSI_LINK_SHIFT_OUT_EN 1 input DFT_IN_PSI_LINK_TEST_EN_N 1 input DFT_IN_PSI_SCAN_MODE_N 1 input DFT_IN_PSI_SI 40 input DFT_IN_PSI_TEST_CLK 1 input DFT_IN_SCANEN_N 1 input DFT_OUT_APS_TEST_SO 4 output DFT_OUT_CLKOD_SCANOUT 1 output DFT_OUT_MAIN_MEM_REF_SO 3 output DFT_OUT_MAIN_MOD_SO 1 output DFT_OUT_MAIN_TDO 1 output DFT_OUT_MAINPLL_CLKOUT 1 output DFT_OUT_MBIST_TDO 1 output DFT_OUT_MPU_TEST_SO 5 output DFT_OUT_OSC_CLKOUT 1 output DFT_OUT_PERI_MEM_REF_SO 3 output DFT_OUT_PERI_MOD_SO 1 output DFT_OUT_PERI_REF_SO 5 output DFT_OUT_PERI_TDO 1 output DFT_OUT_PERIPLL_CLKOUT 1 output DFT_OUT_PSS_TEST_SO 6 output DFT_OUT_RAMRPR_CHAIN0_RSCOUT 1 output DFT_OUT_RAMRPR_CHAIN1_RSCOUT 1 output DFT_OUT_RAMRPR_CHAIN2_RSCOUT 1 output DFT_OUT_RAMRPR_CHAIN3_RSCOUT 1 output DFT_OUT_TDO 1 output DFT_OUT_PSI_SO 1 output DFT_OUT_MAIN_REF_SO 5 output DFT_OUT_TEST_OCC_SO 3 output DFT_OUT_TESTMODE_STATUS_N 1 output DFT_OUT_SPARE_OUT 32 output DFT_IN_MPU_TEST_SI 40 input DFT_IN_OCC_ENABLE_N 1 input DFT_IN_PERI_JTAG_ID 8 input DFT_IN_PERI_JTAG_RST_N 1 input DFT_IN_PERI_MEM_REF_SI 3 input DFT_IN_PERI_MOD_SI 1 input DFT_IN_PERI_PD_N 1 input DFT_IN_PERI_REF_SI 5 input DFT_IN_PERI_RST_N 1 input DFT_IN_PERI_TCK 1 input DFT_IN_PERI_TDI 1 input DFT_IN_PERI_TMS 1 input DFT_IN_PIPELINE_SCAN_EN_N 1 input DFT_IN_PLL_CLK_TESTBUS_SEL 2 input DFT_IN_PLL_DEBUG_TESTBUS_SEL 1 input DFT_IN_PLL_SCAN_MODE_EN 1 input DFT_IN_PLLBYPASS_SEL 1 input DFT_IN_PLLTEST_INPUT_EN 1 input DFT_IN_JTAG_SHFTDR_N 1 input DFT_IN_JTAG_UPDATE_DR_N 1 input DFT_IN_L4MPCLK_DIV_CTL_N 1 input DFT_IN_LOAN_IO_ENABLE_N 1 input DFT_IN_MAIN_JTAG_ID 8 input DFT_IN_MAIN_JTAG_RST_N 1 input DFT_IN_MAIN_MEM_REF_SI 3 input DFT_IN_MAIN_MOD_SI 1 input DFT_IN_MAIN_PD_N 1 input DFT_IN_MAIN_REF_SI 5 input DFT_IN_MAIN_RST_N 1 input DFT_IN_MAIN_SCAN_RST_N 1 input DFT_IN_MAIN_TCK 1 input DFT_IN_MAIN_TDI 1 input DFT_IN_MAIN_TMS 1 input DFT_IN_PSS_TEST_SI 24 input DFT_IN_RAMRPR_CHAIN0_FISO 1 input DFT_IN_RAMRPR_CHAIN0_RSCEN 1 input DFT_IN_RAMRPR_CHAIN0_RSCIN 1 input DFT_IN_RAMRPR_CHAIN0_RSCLK 1 input DFT_IN_RAMRPR_CHAIN0_RSCRST 1 input DFT_IN_RAMRPR_CHAIN1_FISO 1 input DFT_IN_RAMRPR_CHAIN1_RSCEN 1 input DFT_IN_RAMRPR_CHAIN1_RSCIN 1 input DFT_IN_RAMRPR_CHAIN1_RSCLK 1 input DFT_IN_RAMRPR_CHAIN1_RSCRST 1 input DFT_IN_RAMRPR_CHAIN2_FISO 1 input DFT_IN_RAMRPR_CHAIN2_RSCEN 1 input DFT_IN_RAMRPR_CHAIN2_RSCIN 1 input DFT_IN_RAMRPR_CHAIN2_RSCLK 1 input DFT_IN_RAMRPR_CHAIN2_RSCRST 1 input DFT_IN_RAMRPR_CHAIN3_FISO 1 input DFT_IN_RAMRPR_CHAIN3_RSCEN 1 input DFT_IN_RAMRPR_CHAIN3_RSCIN 1 input DFT_IN_RAMRPR_CHAIN3_RSCLK 1 input DFT_IN_RAMRPR_CHAIN3_RSCRST 1 input DFT_IN_RAMRPR_SEL 1 input DFT_IN_S2F_TEST_INPUT 1 input DFT_IN_S2F_TEST_OVERRIDE_N 1 input DFT_IN_SPARE_IN 32 input DFT_IN_TCK 1 input DFT_IN_TDI 1 input DFT_IN_TEST_CLOCK 1 input DFT_IN_TEST_INIT_N 1 input DFT_IN_TEST_OCC_SI 3 input DFT_IN_TEST_RESET_N 1 input DFT_IN_TESTMODE_N 1 input DFT_IN_PERI_SCAN_RST_N 1 input DFT_OUT_PLL_LOCKOUT 1 output} H2F_AXI_CLOCK_FREQ 100000000 I2CEMAC0_PinMuxing Unused MAINPLLGRP_MPU_CNT 2 JAVA_WARNING_MSG {} CLK_SDMMC_SOURCE 0 S2FINTERRUPT_NAND_Enable false LWH2F_ready_latency 0 JAVA_ERROR_MSG {} I2CEMAC2_Mode N/A CLK_EMAC_PTP_SOURCE 1 DB_iface_ports {emac0_tx_clk_in {@orderednames emac0_clk_tx_i emac0_clk_tx_i {direction Input atom_signal_name phy_txclk_i role clk}} emac0_gtx_clk {emac0_phy_txclk_o {direction Output atom_signal_name phy_txclk_o_hio role clk} @orderednames emac0_phy_txclk_o} spim0 {spim0_ss3_n_o {direction Output atom_signal_name ss3_n_o role ss3_n_o} spim0_miso_i {direction Input atom_signal_name miso_i role miso_i} @orderednames {spim0_mosi_o spim0_miso_i spim0_ss_in_n spim0_mosi_oe spim0_ss0_n_o spim0_ss1_n_o spim0_ss2_n_o spim0_ss3_n_o} spim0_ss_in_n {direction Input atom_signal_name ss_in_n role ss_in_n} spim0_ss0_n_o {direction Output atom_signal_name ss0_n_o role ss0_n_o} spim0_ss1_n_o {direction Output atom_signal_name ss1_n_o role ss1_n_o} spim0_mosi_o {direction Output atom_signal_name mosi_o role mosi_o} spim0_mosi_oe {direction Output atom_signal_name mosi_oe role mosi_oe} spim0_ss2_n_o {direction Output atom_signal_name ss2_n_o role ss2_n_o}} emac1_gtx_clk {@orderednames emac1_phy_txclk_o emac1_phy_txclk_o {direction Output atom_signal_name phy_txclk_o_hio role clk}} spim1 {spim1_mosi_oe {direction Output atom_signal_name mosi_oe role mosi_oe} spim1_ss2_n_o {direction Output atom_signal_name ss2_n_o role ss2_n_o} spim1_ss3_n_o {direction Output atom_signal_name ss3_n_o role ss3_n_o} spim1_miso_i {direction Input atom_signal_name miso_i role miso_i} @orderednames {spim1_mosi_o spim1_miso_i spim1_ss_in_n spim1_mosi_oe spim1_ss0_n_o spim1_ss1_n_o spim1_ss2_n_o spim1_ss3_n_o} spim1_ss_in_n {direction Input atom_signal_name ss_in_n role ss_in_n} spim1_ss0_n_o {direction Output atom_signal_name ss0_n_o role ss0_n_o} spim1_ss1_n_o {direction Output atom_signal_name ss1_n_o role ss1_n_o} spim1_mosi_o {direction Output atom_signal_name mosi_o role mosi_o}} emac2_gtx_clk {@orderednames emac2_phy_txclk_o emac2_phy_txclk_o {direction Output atom_signal_name phy_txclk_o_hio role clk}} i2cemac1_scl_in {i2c_emac1_scl_i {direction Input atom_signal_name scl_i role clk} @orderednames i2c_emac1_scl_i} spim0_sclk_out {spim0_sclk_out {direction Output atom_signal_name sclk_out_hio role clk} @orderednames spim0_sclk_out} i2cemac1_clk {i2c_emac1_scl_oe {direction Output atom_signal_name scl_oe role clk} @orderednames i2c_emac1_scl_oe} emac0 {emac0_ptp_aux_ts_trig_i {direction Input atom_signal_name ptp_aux_ts_trig_i role ptp_aux_ts_trig_i} emac0_ptp_pps_o {direction Output atom_signal_name ptp_pps_o role ptp_pps_o} @orderednames {emac0_phy_txd_o emac0_phy_mac_speed_o emac0_phy_txen_o emac0_phy_txer_o emac0_phy_rxdv_i emac0_phy_rxer_i emac0_phy_rxd_i emac0_phy_col_i emac0_phy_crs_i emac0_gmii_mdo_o emac0_gmii_mdo_o_e emac0_gmii_mdi_i emac0_ptp_pps_o emac0_ptp_aux_ts_trig_i emac0_ptp_tstmp_data emac0_ptp_tstmp_en} emac0_phy_rxdv_i {direction Input atom_signal_name phy_rxdv_i role phy_rxdv_i} emac0_phy_rxd_i {direction Input atom_signal_name phy_rxd_i role phy_rxd_i} emac0_phy_mac_speed_o {direction Output atom_signal_name phy_mac_speed_o role phy_mac_speed_o} emac0_gmii_mdo_o_e {direction Output atom_signal_name gmii_mdo_o_e role gmii_mdo_o_e} emac0_phy_rxer_i {direction Input atom_signal_name phy_rxer_i role phy_rxer_i} emac0_gmii_mdo_o {direction Output atom_signal_name gmii_mdo_o role gmii_mdo_o} emac0_ptp_tstmp_data {direction Output atom_signal_name ptp_tstmp_data role ptp_tstmp_data} emac0_ptp_tstmp_en {direction Output atom_signal_name ptp_tstmp_en role ptp_tstmp_en} emac0_phy_txen_o {direction Output atom_signal_name phy_txen_o role phy_txen_o} emac0_phy_txd_o {direction Output atom_signal_name phy_txd_o role phy_txd_o} emac0_phy_col_i {direction Input atom_signal_name phy_col_i role phy_col_i} emac0_gmii_mdi_i {direction Input atom_signal_name gmii_mdi_i role gmii_mdi_i} emac0_phy_crs_i {direction Input atom_signal_name phy_crs_i role phy_crs_i} emac0_phy_txer_o {direction Output atom_signal_name phy_txer_o role phy_txer_o}} emac1 {emac1_gmii_mdo_o {direction Output atom_signal_name gmii_mdo_o role gmii_mdo_o} @orderednames {emac1_phy_mac_speed_o emac1_phy_txd_o emac1_phy_txen_o emac1_phy_txer_o emac1_phy_rxdv_i emac1_phy_rxer_i emac1_phy_rxd_i emac1_phy_col_i emac1_phy_crs_i emac1_gmii_mdo_o emac1_gmii_mdo_o_e emac1_gmii_mdi_i emac1_ptp_pps_o emac1_ptp_aux_ts_trig_i emac1_ptp_tstmp_data emac1_ptp_tstmp_en} emac1_ptp_tstmp_data {direction Output atom_signal_name ptp_tstmp_data role ptp_tstmp_data} emac1_ptp_aux_ts_trig_i {direction Input atom_signal_name ptp_aux_ts_trig_i role ptp_aux_ts_trig_i} emac1_ptp_pps_o {direction Output atom_signal_name ptp_pps_o role ptp_pps_o} emac1_ptp_tstmp_en {direction Output atom_signal_name ptp_tstmp_en role ptp_tstmp_en} emac1_phy_txen_o {direction Output atom_signal_name phy_txen_o role phy_txen_o} emac1_phy_rxd_i {direction Input atom_signal_name phy_rxd_i role phy_rxd_i} emac1_gmii_mdi_i {direction Input atom_signal_name gmii_mdi_i role gmii_mdi_i} emac1_phy_mac_speed_o {direction Output atom_signal_name phy_mac_speed_o role phy_mac_speed_o} emac1_phy_txer_o {direction Output atom_signal_name phy_txer_o role phy_txer_o} emac1_phy_rxdv_i {direction Input atom_signal_name phy_rxdv_i role phy_rxdv_i} emac1_phy_txd_o {direction Output atom_signal_name phy_txd_o role phy_txd_o} emac1_phy_col_i {direction Input atom_signal_name phy_col_i role phy_col_i} emac1_gmii_mdo_o_e {direction Output atom_signal_name gmii_mdo_o_e role gmii_mdo_o_e} emac1_phy_crs_i {direction Input atom_signal_name phy_crs_i role phy_crs_i} emac1_phy_rxer_i {direction Input atom_signal_name phy_rxer_i role phy_rxer_i}} emac2 {emac2_phy_txer_o {direction Output atom_signal_name phy_txer_o role phy_txer_o} @orderednames {emac2_phy_mac_speed_o emac2_phy_txd_o emac2_phy_txen_o emac2_phy_txer_o emac2_phy_rxdv_i emac2_phy_rxer_i emac2_phy_rxd_i emac2_phy_col_i emac2_phy_crs_i emac2_gmii_mdo_o emac2_gmii_mdo_o_e emac2_gmii_mdi_i emac2_ptp_pps_o emac2_ptp_aux_ts_trig_i emac2_ptp_tstmp_data emac2_ptp_tstmp_en} emac2_ptp_aux_ts_trig_i {direction Input atom_signal_name ptp_aux_ts_trig_i role ptp_aux_ts_trig_i} emac2_ptp_pps_o {direction Output atom_signal_name ptp_pps_o role ptp_pps_o} emac2_phy_rxdv_i {direction Input atom_signal_name phy_rxdv_i role phy_rxdv_i} emac2_phy_rxd_i {direction Input atom_signal_name phy_rxd_i role phy_rxd_i} emac2_phy_mac_speed_o {direction Output atom_signal_name phy_mac_speed_o role phy_mac_speed_o} emac2_gmii_mdo_o_e {direction Output atom_signal_name gmii_mdo_o_e role gmii_mdo_o_e} emac2_phy_rxer_i {direction Input atom_signal_name phy_rxer_i role phy_rxer_i} emac2_gmii_mdo_o {direction Output atom_signal_name gmii_mdo_o role gmii_mdo_o} emac2_ptp_tstmp_data {direction Output atom_signal_name ptp_tstmp_data role ptp_tstmp_data} emac2_ptp_tstmp_en {direction Output atom_signal_name ptp_tstmp_en role ptp_tstmp_en} emac2_phy_txen_o {direction Output atom_signal_name phy_txen_o role phy_txen_o} emac2_phy_col_i {direction Input atom_signal_name phy_col_i role phy_col_i} emac2_phy_txd_o {direction Output atom_signal_name phy_txd_o role phy_txd_o} emac2_gmii_mdi_i {direction Input atom_signal_name gmii_mdi_i role gmii_mdi_i} emac2_phy_crs_i {direction Input atom_signal_name phy_crs_i role phy_crs_i}} spis0_sclk_in {spis0_sclk_in {direction Input atom_signal_name clk role clk} @orderednames spis0_sclk_in} spis1_sclk_in {@orderednames spis1_sclk_in spis1_sclk_in {direction Input atom_signal_name clk role clk}} trace_s2f_clk {@orderednames trace_s2f_clk trace_s2f_clk {direction Output atom_signal_name trace_clk_hio role clk}} emac0_tx_reset {emac0_rst_clk_tx_n_o {direction Output atom_signal_name rst_clk_tx_n_o role reset_n} @orderednames emac0_rst_clk_tx_n_o} i2cemac0_scl_in {i2c_emac0_scl_i {direction Input atom_signal_name scl_i role clk} @orderednames i2c_emac0_scl_i} sdmmc {@orderednames {sdmmc_vs_o sdmmc_pwr_ena_o sdmmc_wp_i sdmmc_cdn_i sdmmc_card_intn_i sdmmc_cmd_i sdmmc_cmd_o sdmmc_cmd_oe sdmmc_data_i sdmmc_data_o sdmmc_data_oe} sdmmc_cmd_oe {direction Output atom_signal_name cmd_oe role cmd_oe} sdmmc_pwr_ena_o {direction Output atom_signal_name pwr_ena_o role pwr_ena_o} sdmmc_card_intn_i {direction Input atom_signal_name card_intn_i role card_intn_i} sdmmc_cmd_o {direction Output atom_signal_name cmd_o role cmd_o} sdmmc_data_i {direction Input atom_signal_name data_i role data_i} sdmmc_cdn_i {direction Input atom_signal_name cdn_i role cdn_i} sdmmc_data_oe {direction Output atom_signal_name data_oe role data_oe} sdmmc_vs_o {direction Output atom_signal_name vs_o role vs_o} sdmmc_wp_i {direction Input atom_signal_name wp_i role wp_i} sdmmc_data_o {direction Output atom_signal_name data_o role data_o} sdmmc_cmd_i {direction Input atom_signal_name cmd_i role cmd_i}} spim1_sclk_out {spim1_sclk_out {direction Output atom_signal_name sclk_out_hio role clk} @orderednames spim1_sclk_out} emac1_rx_clk_in {emac1_clk_rx_i {direction Input atom_signal_name phy_rxclk_i role clk} @orderednames emac1_clk_rx_i} i2c0_clk {@orderednames i2c0_scl_oe i2c0_scl_oe {direction Output atom_signal_name scl_oe role clk}} emac1_tx_clk_in {@orderednames emac1_clk_tx_i emac1_clk_tx_i {direction Input atom_signal_name phy_txclk_i role clk}} i2cemac0 {i2c_emac0_sda_oe {direction Output atom_signal_name sda_oe role sda_oe} @orderednames {i2c_emac0_sda_i i2c_emac0_sda_oe} i2c_emac0_sda_i {direction Input atom_signal_name sda_i role sda_i}} emac1_tx_reset {@orderednames emac1_rst_clk_tx_n_o emac1_rst_clk_tx_n_o {direction Output atom_signal_name rst_clk_tx_n_o role reset_n}} i2cemac1 {@orderednames {i2c_emac1_sda_i i2c_emac1_sda_oe} i2c_emac1_sda_oe {direction Output atom_signal_name sda_oe role sda_oe} i2c_emac1_sda_i {direction Input atom_signal_name sda_i role sda_i}} i2cemac2 {i2c_emac2_sda_i {direction Input atom_signal_name sda_i role sda_i} @orderednames {i2c_emac2_sda_i i2c_emac2_sda_oe} i2c_emac2_sda_oe {direction Output atom_signal_name sda_oe role sda_oe}} emac0_rx_reset {@orderednames emac0_rst_clk_rx_n_o emac0_rst_clk_rx_n_o {direction Output atom_signal_name rst_clk_rx_n_o role reset_n}} emac2_tx_reset {@orderednames emac2_rst_clk_tx_n_o emac2_rst_clk_tx_n_o {direction Output atom_signal_name rst_clk_tx_n_o role reset_n}} i2c1_scl_in {i2c1_scl_i {direction Input atom_signal_name scl_i role clk} @orderednames i2c1_scl_i} emac2_rx_clk_in {@orderednames emac2_clk_rx_i emac2_clk_rx_i {direction Input atom_signal_name phy_rxclk_i role clk}} sdmmc_cclk {@orderednames sdmmc_cclk_out sdmmc_cclk_out {direction Output atom_signal_name cclk_o role clk}} emac2_md_clk {@orderednames emac2_gmii_mdc_o emac2_gmii_mdc_o {direction Output atom_signal_name gmii_mdc_o role clk}} emac1_rx_reset {emac1_rst_clk_rx_n_o {direction Output atom_signal_name rst_clk_rx_n_o role reset_n} @orderednames emac1_rst_clk_rx_n_o} emac2_tx_clk_in {emac2_clk_tx_i {direction Input atom_signal_name phy_txclk_i role clk} @orderednames emac2_clk_tx_i} uart0 {uart0_out1_n {direction Output atom_signal_name out1_n role out1_n} uart0_dsr_n {direction Input atom_signal_name dsr_n role dsr_n} @orderednames {uart0_cts_n uart0_dsr_n uart0_dcd_n uart0_ri_n uart0_rx uart0_dtr_n uart0_rts_n uart0_out1_n uart0_out2_n uart0_tx} uart0_rx {direction Input atom_signal_name rx role rx} uart0_rts_n {direction Output atom_signal_name rts_n role rts_n} uart0_dtr_n {direction Output atom_signal_name dtr_n role dtr_n} uart0_cts_n {direction Input atom_signal_name cts_n role cts_n} uart0_out2_n {direction Output atom_signal_name out2_n role out2_n} uart0_tx {direction Output atom_signal_name tx role tx} uart0_ri_n {direction Input atom_signal_name ri_n role ri_n} uart0_dcd_n {direction Input atom_signal_name dcd_n role dcd_n}} i2cemac0_clk {@orderednames i2c_emac0_scl_oe i2c_emac0_scl_oe {direction Output atom_signal_name scl_oe role clk}} uart1 {uart1_tx {direction Output atom_signal_name tx role tx} uart1_ri_n {direction Input atom_signal_name ri_n role ri_n} uart1_dcd_n {direction Input atom_signal_name dcd_n role dcd_n} @orderednames {uart1_cts_n uart1_dsr_n uart1_dcd_n uart1_ri_n uart1_rx uart1_dtr_n uart1_rts_n uart1_out1_n uart1_out2_n uart1_tx} uart1_out1_n {direction Output atom_signal_name out1_n role out1_n} uart1_dsr_n {direction Input atom_signal_name dsr_n role dsr_n} uart1_rx {direction Input atom_signal_name rx role rx} uart1_rts_n {direction Output atom_signal_name rts_n role rts_n} uart1_dtr_n {direction Output atom_signal_name dtr_n role dtr_n} uart1_cts_n {direction Input atom_signal_name cts_n role cts_n} uart1_out2_n {direction Output atom_signal_name out2_n role out2_n}} i2c0_scl_in {@orderednames i2c0_scl_i i2c0_scl_i {direction Input atom_signal_name scl_i role clk}} i2cemac2_clk {i2c_emac2_scl_oe {direction Output atom_signal_name scl_oe role clk} @orderednames i2c_emac2_scl_oe} trace {trace_data {direction Output atom_signal_name trace_data role data} @orderednames {trace_clk_ctl trace_clkin trace_data} trace_clk_ctl {direction Input atom_signal_name trace_ctl role clk_ctl} trace_clkin {direction Input atom_signal_name trace_clkin role clkin}} emac1_md_clk {emac1_gmii_mdc_o {direction Output atom_signal_name gmii_mdc_o role clk} @orderednames emac1_gmii_mdc_o} emac2_rx_reset {emac2_rst_clk_rx_n_o {direction Output atom_signal_name rst_clk_rx_n_o role reset_n} @orderednames emac2_rst_clk_rx_n_o} emac0_md_clk {emac0_gmii_mdc_o {direction Output atom_signal_name gmii_mdc_o role clk} @orderednames emac0_gmii_mdc_o} i2c1_clk {@orderednames i2c1_scl_oe i2c1_scl_oe {direction Output atom_signal_name scl_oe role clk}} nand {nand_ale_o {direction Output atom_signal_name ale_o role ale_o} nand_adq_o {direction Output atom_signal_name adq_o role adq_o} nand_wp_o {direction Output atom_signal_name wp_n_o role wp_n_o} nand_rdy_busy_i {direction Input atom_signal_name rdy_busy_i role rdy_busy_i} nand_adq_oe {direction Output atom_signal_name adq_oe role adq_oe} @orderednames {nand_adq_i nand_adq_oe nand_adq_o nand_ale_o nand_ce_o nand_cle_o nand_re_o nand_rdy_busy_i nand_we_o nand_wp_o} nand_re_o {direction Output atom_signal_name re_n_o role re_n_o} nand_cle_o {direction Output atom_signal_name cle_o role cle_o} nand_adq_i {direction Input atom_signal_name adq_i role adq_i} nand_ce_o {direction Output atom_signal_name ce_n_o role ce_n_o} nand_we_o {direction Output atom_signal_name we_n_o role we_n_o}} usb0 {usb0_ulpi_nxt {direction Input atom_signal_name ulpi_nxt role ulpi_nxt} usb0_ulpi_data_i {direction Input atom_signal_name ulpi_data_i role ulpi_data_i} usb0_ulpi_stp {direction Output atom_signal_name ulpi_stp role ulpi_stp} @orderednames {usb0_ulpi_dir usb0_ulpi_nxt usb0_ulpi_data_i usb0_ulpi_stp usb0_ulpi_data_o usb0_ulpi_data_oe} usb0_ulpi_dir {direction Input atom_signal_name ulpi_dir role ulpi_dir} usb0_ulpi_data_o {direction Output atom_signal_name ulpi_data_o role ulpi_data_o} usb0_ulpi_data_oe {direction Output atom_signal_name ulpi_data_oe role ulpi_data_oe}} usb1_clk_in {usb1_ulpi_clk {direction Input atom_signal_name ulpi_clk role clk} @orderednames usb1_ulpi_clk} usb1 {usb1_ulpi_data_oe {direction Output atom_signal_name ulpi_data_oe role ulpi_data_oe} usb1_ulpi_nxt {direction Input atom_signal_name ulpi_nxt role ulpi_nxt} @orderednames {usb1_ulpi_dir usb1_ulpi_nxt usb1_ulpi_data_i usb1_ulpi_stp usb1_ulpi_data_o usb1_ulpi_data_oe} usb1_ulpi_data_i {direction Input atom_signal_name ulpi_data_i role ulpi_data_i} usb1_ulpi_stp {direction Output atom_signal_name ulpi_stp role ulpi_stp} usb1_ulpi_dir {direction Input atom_signal_name ulpi_dir role ulpi_dir} usb1_ulpi_data_o {direction Output atom_signal_name ulpi_data_o role ulpi_data_o}} sdmmc_reset {sdmmc_rstn_o {direction Output atom_signal_name rstn_o role reset} @orderednames sdmmc_rstn_o} spis0 {spis0_miso_o {direction Output atom_signal_name miso_o role miso_o} spis0_miso_oe {direction Output atom_signal_name miso_oe role miso_oe} @orderednames {spis0_mosi_i spis0_ss_in_n spis0_miso_o spis0_miso_oe} spis0_mosi_i {direction Input atom_signal_name mosi_i role mosi_i} spis0_ss_in_n {direction Input atom_signal_name ss_in_n role ss_in_n}} spis1 {spis1_ss_in_n {direction Input atom_signal_name ss_in_n role ss_in_n} @orderednames {spis1_mosi_i spis1_ss_in_n spis1_miso_o spis1_miso_oe} spis1_miso_o {direction Output atom_signal_name miso_o role miso_o} spis1_miso_oe {direction Output atom_signal_name miso_oe role miso_oe} spis1_mosi_i {direction Input atom_signal_name mosi_i role mosi_i}} usb0_clk_in {usb0_ulpi_clk {direction Input atom_signal_name ulpi_clk role clk} @orderednames usb0_ulpi_clk} i2cemac2_scl_in {@orderednames i2c_emac2_scl_i i2c_emac2_scl_i {direction Input atom_signal_name scl_i role clk}} emac0_rx_clk_in {emac0_clk_rx_i {direction Input atom_signal_name phy_rxclk_i role clk} @orderednames emac0_clk_rx_i} i2c0 {i2c0_sda_oe {direction Output atom_signal_name sda_oe role sda_oe} @orderednames {i2c0_sda_i i2c0_sda_oe} i2c0_sda_i {direction Input atom_signal_name sda_i role sda_i}} i2c1 {i2c1_sda_oe {direction Output atom_signal_name sda_oe role sda_oe} @orderednames {i2c1_sda_i i2c1_sda_oe} i2c1_sda_i {direction Input atom_signal_name sda_i role sda_i}}} EMAC2_Mode RGMII_with_MDIO CLK_NOC_CNT 0 DB_periph_ifaces {@orderednames {EMAC0 EMAC1 EMAC2 NAND SDMMC USB0 USB1 SPIM0 SPIM1 SPIS0 SPIS1 TRACE UART0 UART1 I2C0 I2C1 I2CEMAC0 I2CEMAC1 I2CEMAC2} NAND {interfaces {nand {properties {} direction Input @no_export 0 type conduit} @orderednames nand} atom_name hps_interface_peripheral_nand} SPIM0 {interfaces {spim0_sclk_out {properties {} direction Output @no_export 0 type clock} @orderednames {spim0 spim0_sclk_out} spim0 {properties {} direction Input @no_export 0 type conduit}} atom_name hps_interface_peripheral_spi_master} USB0 {interfaces {usb0_clk_in {properties {} direction Input @no_export 0 type clock} @orderednames {usb0 usb0_clk_in} usb0 {properties {} direction Input @no_export 0 type conduit}}} SPIM1 {interfaces {spim1_sclk_out {properties {} direction Output @no_export 0 type clock} @orderednames {spim1 spim1_sclk_out} spim1 {properties {} direction Input @no_export 0 type conduit}} atom_name hps_interface_peripheral_spi_master} USB1 {interfaces {@orderednames {usb1 usb1_clk_in} usb1_clk_in {properties {} direction Input @no_export 0 type clock} usb1 {properties {} direction Input @no_export 0 type conduit}}} I2CEMAC0 {interfaces {i2cemac0 {properties {} direction Input @no_export 0 type conduit} @orderednames {i2cemac0_scl_in i2cemac0_clk i2cemac0} i2cemac0_clk {properties {} direction Output @no_export 0 type clock} i2cemac0_scl_in {properties {} direction Input @no_export 0 type clock}} atom_name hps_interface_peripheral_i2c} UART0 {interfaces {uart0 {properties {} direction Input @no_export 0 type conduit} @orderednames uart0} atom_name hps_interface_peripheral_uart} I2CEMAC1 {interfaces {i2cemac1_scl_in {properties {} direction Input @no_export 0 type clock} i2cemac1 {properties {} direction Input @no_export 0 type conduit} @orderednames {i2cemac1_scl_in i2cemac1_clk i2cemac1} i2cemac1_clk {properties {} direction Output @no_export 0 type clock}} atom_name hps_interface_peripheral_i2c} UART1 {interfaces {uart1 {properties {} direction Input @no_export 0 type conduit} @orderednames uart1} atom_name hps_interface_peripheral_uart} I2CEMAC2 {interfaces {i2cemac2_scl_in {properties {} direction Input @no_export 0 type clock} @orderednames {i2cemac2_scl_in i2cemac2_clk i2cemac2} i2cemac2 {properties {} direction Input @no_export 0 type conduit} i2cemac2_clk {properties {} direction Output @no_export 0 type clock}} atom_name hps_interface_peripheral_i2c} EMAC0 {interfaces {emac0_tx_clk_in {properties {} direction Input @no_export 0 type clock} emac0_rx_reset {properties {associatedClock emac0_rx_clk_in associatedResetSinks none} direction Output @no_export 0 type reset} emac0_gtx_clk {properties {} direction Output @no_export 0 type clock} @orderednames {emac0 emac0_md_clk emac0_rx_clk_in emac0_tx_clk_in emac0_gtx_clk emac0_tx_reset emac0_rx_reset} emac0_rx_clk_in {properties {} direction Input @no_export 0 type clock} emac0 {properties {} direction Input @no_export 0 type conduit} emac0_md_clk {properties {} direction Output @no_export 0 type clock} emac0_tx_reset {properties {associatedClock emac0_tx_clk_in associatedResetSinks none} direction Output @no_export 0 type reset}} atom_name hps_interface_peripheral_emac} TRACE {interfaces {@orderednames {trace_s2f_clk trace} trace_s2f_clk {properties {} direction Output @no_export 0 type clock} trace {properties {} direction Input @no_export 0 type conduit}} atom_name hps_interface_tpiu_trace} EMAC1 {interfaces {emac1_md_clk {properties {} direction Output @no_export 0 type clock} emac1_tx_reset {properties {associatedClock emac1_tx_clk_in associatedResetSinks none} direction Output @no_export 0 type reset} @orderednames {emac1 emac1_md_clk emac1_rx_clk_in emac1_tx_clk_in emac1_gtx_clk emac1_tx_reset emac1_rx_reset} emac1_tx_clk_in {properties {} direction Input @no_export 0 type clock} emac1_rx_reset {properties {associatedClock emac1_rx_clk_in associatedResetSinks none} direction Output @no_export 0 type reset} emac1_gtx_clk {properties {} direction Output @no_export 0 type clock} emac1_rx_clk_in {properties {} direction Input @no_export 0 type clock} emac1 {properties {} direction Input @no_export 0 type conduit}} atom_name hps_interface_peripheral_emac} SPIS0 {interfaces {spis0_sclk_in {properties {} direction Input @no_export 0 type clock} @orderednames {spis0 spis0_sclk_in} spis0 {properties {} direction Input @no_export 0 type conduit}} atom_name hps_interface_peripheral_spi_slave} EMAC2 {interfaces {emac2_rx_clk_in {properties {} direction Input @no_export 0 type clock} emac2 {properties {} direction Input @no_export 0 type conduit} @orderednames {emac2 emac2_md_clk emac2_rx_clk_in emac2_tx_clk_in emac2_gtx_clk emac2_tx_reset emac2_rx_reset} emac2_md_clk {properties {} direction Output @no_export 0 type clock} emac2_tx_reset {properties {associatedClock emac2_tx_clk_in associatedResetSinks none} direction Output @no_export 0 type reset} emac2_tx_clk_in {properties {} direction Input @no_export 0 type clock} emac2_rx_reset {properties {associatedClock emac2_rx_clk_in associatedResetSinks none} direction Output @no_export 0 type reset} emac2_gtx_clk {properties {} direction Output @no_export 0 type clock}} atom_name hps_interface_peripheral_emac} SPIS1 {interfaces {spis1 {properties {} direction Input @no_export 0 type conduit} @orderednames {spis1 spis1_sclk_in} spis1_sclk_in {properties {} direction Input @no_export 0 type clock}} atom_name hps_interface_peripheral_spi_slave} SDMMC {interfaces {sdmmc_cclk {properties {} direction Output @no_export 0 type clock} sdmmc {properties {} direction Input @no_export 0 type conduit} @orderednames {sdmmc sdmmc_reset sdmmc_cclk} sdmmc_reset {properties {synchronousEdges none} direction Output @no_export 0 type reset}} atom_name hps_interface_peripheral_sdmmc} I2C0 {interfaces {i2c0_scl_in {properties {} direction Input @no_export 0 type clock} @orderednames {i2c0_scl_in i2c0_clk i2c0} i2c0 {properties {} direction Input @no_export 0 type conduit} i2c0_clk {properties {} direction Output @no_export 0 type clock}} atom_name hps_interface_peripheral_i2c} I2C1 {interfaces {i2c1_clk {properties {} direction Output @no_export 0 type clock} @orderednames {i2c1_scl_in i2c1_clk i2c1} i2c1_scl_in {properties {} direction Input @no_export 0 type clock} i2c1 {properties {} direction Input @no_export 0 type conduit}} atom_name hps_interface_peripheral_i2c}} NOCDIV_L4SPCLK 2 SDMMC_Mode 4-bit UART0_PinMuxing IO F2S_Width 3 dev_database {} FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM1_SCLK_OUT 100 DDR_ATB_Enable false F2H_SDRAM0_CLOCK_FREQ 100 NOCDIV_CS_ATCLK 0 EMAC2_SWITCH_Enable false F2S_mode 0 CLK_MPU_CNT 0 S2FINTERRUPT_USB1_Enable false SDMMC_PinMuxing IO F2SDRAM0_ready_latency 0 CLK_S2F_USER0_SOURCE 1 MAINPLLGRP_S2F_USER0_CNT 999 DB_port_pins {spim0_miso_i {0 rxd} usb0_ulpi_stp {0 ulpi_stp} emac0_ptp_aux_ts_trig_i {0 ts_trig} uart1_dsr_n {0 dsr_n} spim0_ss1_n_o {0 ss_cs1} emac1_ptp_pps_o {0 ptp_pps} emac1_phy_txclk_o {0 tx_clk_o} spim1_ss1_n_o {0 ss_cs1} emac0_phy_rxd_i {0 rxd0 4 rxd4 5 rxd5 1 rxd1 2 rxd2 6 rxd6 7 rxd7 3 rxd3} emac1_ptp_tstmp_en {0 ptp_tstmp_en} emac1_clk_tx_i {0 tx_clk_i} uart1_dcd_n {0 dcd_n} spim0_ss3_n_o {0 ss_cs3} spim0_sclk_out {0 sclk_out} spis1_miso_o {0 txd} spim1_ss3_n_o {0 ss_cs3} emac1_gmii_mdi_i {0 mdi} emac0_phy_rxer_i {0 rxer} emac1_rst_clk_tx_n_o {0 rst_clk_tx_n_o} emac0_clk_rx_i {0 rx_clk} uart0_rts_n {0 rts_n} spis0_sclk_in {0 sclk_in} trace_s2f_clk {0 s2f_clk} i2c_emac0_sda_i {0 ic_data_in_a} spis1_sclk_in {0 sclk_in} usb1_ulpi_stp {0 ulpi_stp} emac2_gmii_mdo_o {0 mdo} emac1_phy_rxdv_i {0 rxdv} i2c1_scl_oe {0 ic_clk_oe} uart1_cts_n {0 cts_n} emac0_phy_txd_o {0 txd0 4 txd4 5 txd5 1 txd1 2 txd2 6 txd6 7 txd7 3 txd3} uart1_ri_n {0 ri_n} spis0_miso_o {0 txd} emac2_clk_tx_i {0 tx_clk_i} emac0_gmii_mdc_o {0 mdc} emac1_phy_col_i {0 col} emac2_phy_txen_o {0 txen} uart0_rx {0 sin} spim1_sclk_out {0 sclk_out} emac0_rst_clk_tx_n_o {0 rst_clk_tx_n_o} i2c_emac2_scl_i {0 ic_clk_in_a} i2c1_sda_i {0 ic_data_in_a} emac1_phy_crs_i {0 crs} usb0_ulpi_data_oe {0 ulpi_data_out_en0 4 ulpi_data_out_en4 5 ulpi_data_out_en5 1 ulpi_data_out_en1 2 ulpi_data_out_en2 6 ulpi_data_out_en6 7 ulpi_data_out_en7 3 ulpi_data_out_en3} sdmmc_cmd_i {0 ccmd_i} emac2_phy_txer_o {0 txer} uart0_dsr_n {0 dsr_n} spis0_miso_oe {0 ssi_oe_n} emac1_clk_rx_i {0 rx_clk} i2c0_scl_oe {0 ic_clk_oe} spis1_miso_oe {0 ssi_oe_n} emac1_ptp_aux_ts_trig_i {0 ts_trig} uart0_dcd_n {0 dcd_n} emac2_ptp_pps_o {0 ptp_pps} usb0_ulpi_data_i {0 ulpi_datain0 4 ulpi_datain4 5 ulpi_datain5 1 ulpi_datain1 2 ulpi_datain2 6 ulpi_datain6 7 ulpi_datain7 3 ulpi_datain3} usb0_ulpi_nxt {0 ulpi_nxt} emac0_gmii_mdo_o_e {0 mdo_en} emac0_phy_mac_speed_o {0 mac_speed0 1 mac_speed1} emac1_phy_rxd_i {0 rxd0 4 rxd4 5 rxd5 1 rxd1 2 rxd2 6 rxd6 7 rxd7 3 rxd3} sdmmc_cmd_o {0 ccmd_o} sdmmc_card_intn_i {0 card_int_n} sdmmc_pwr_ena_o {0 pwer_en_o} emac1_phy_mac_speed_o {0 mac_speed0 1 mac_speed1} emac2_phy_mac_speed_o {0 mac_speed0 1 mac_speed1} sdmmc_cclk_out {0 cclk_out} sdmmc_rstn_o {0 rst_out_n} sdmmc_cdn_i {0 cd_i_n} emac0_gmii_mdo_o {0 mdo} i2c_emac2_scl_oe {0 ic_clk_oe} i2c1_sda_oe {0 ic_data_oe} uart0_cts_n {0 cts_n} usb0_ulpi_data_o {0 ulpi_dataout0 4 ulpi_dataout4 5 ulpi_dataout5 1 ulpi_dataout1 2 ulpi_dataout2 6 ulpi_dataout6 7 ulpi_dataout7 3 ulpi_dataout3} sdmmc_vs_o {0 vs_o} emac2_clk_rx_i {0 rx_clk} emac0_phy_txen_o {0 txen} emac0_ptp_tstmp_en {0 ptp_tstmp_en} uart1_dtr_n {0 dtr_n} emac1_phy_txd_o {0 txd0 4 txd4 5 txd5 1 txd1 2 txd2 6 txd6 7 txd7 3 txd3} i2c_emac1_scl_i {0 ic_clk_in_a} i2c0_sda_i {0 ic_data_in_a} usb1_ulpi_nxt {0 ulpi_nxt} emac2_phy_col_i {0 col} nand_adq_i {0 adq_in0 1 adq_in1 2 adq_in2 3 adq_in3 4 adq_in4 5 adq_in5 6 adq_in6 7 adq_in7 8 adq_in8 10 adq_in10 9 adq_in9 11 adq_in11 12 adq_in12 13 adq_in13 14 adq_in14 15 adq_in15} emac2_gmii_mdi_i {0 mdi} emac0_phy_txer_o {0 txer} uart0_tx {0 sout} spis1_mosi_i {0 rxd} spis0_ss_in_n {0 ss_in_n} spim1_mosi_o {0 txd} emac2_phy_crs_i {0 crs} emac1_phy_rxer_i {0 rxer} i2c_emac1_scl_oe {0 ic_clk_oe} i2c0_sda_oe {0 ic_data_oe} spis1_ss_in_n {0 ss_in_n} nand_ale_o {0 ale_out} spim0_ss0_n_o {0 ss_cs0} usb0_ulpi_dir {0 ulpi_dir} emac0_phy_txclk_o {0 tx_clk_o} uart1_out1_n {0 out1_n} spim1_ss0_n_o {0 ss_cs0} sdmmc_cmd_oe {0 ccmd_en} nand_cle_o {0 cle_out} uart0_ri_n {0 ri_n} spim0_ss2_n_o {0 ss_cs2} emac2_phy_txclk_o {0 tx_clk_o} emac2_ptp_aux_ts_trig_i {0 ts_trig} emac2_phy_rxdv_i {0 rxdv} spim1_ss2_n_o {0 ss_cs2} usb0_ulpi_clk {0 ulpi_clk} nand_adq_o {0 adq_out0 1 adq_out1 2 adq_out2 3 adq_out3 4 adq_out4 5 adq_out5 6 adq_out6 7 adq_out7 8 adq_out8 10 adq_out10 9 adq_out9 11 adq_out11 12 adq_out12 13 adq_out13 14 adq_out14 15 adq_out15} sdmmc_data_i {0 cdata_in0 4 cdata_in4 5 cdata_in5 1 cdata_in1 2 cdata_in2 6 cdata_in6 7 cdata_in7 3 cdata_in3} emac2_phy_rxd_i {0 rxd0 4 rxd4 5 rxd5 1 rxd1 2 rxd2 6 rxd6 7 rxd7 3 rxd3} emac1_gmii_mdc_o {0 mdc} uart1_rx {0 sin} spis0_mosi_i {0 rxd} spim0_mosi_o {0 txd} emac2_gmii_mdo_o_e {0 mdo_en} i2c_emac2_sda_oe {0 ic_data_oe} i2c_emac0_scl_oe {0 ic_clk_oe} trace_data {35 d35 36 d36 37 d37 38 d38 40 d40 39 d39 41 d41 42 d42 43 d43 44 d44 45 d45 46 d46 47 d47 48 d48 50 d50 49 d49 51 d51 52 d52 53 d53 54 d54 55 d55 56 d56 57 d57 58 d58 60 d60 59 d59 61 d61 62 d62 63 d63 10 d10 11 d11 12 d12 13 d13 14 d14 15 d15 16 d16 0 d0 17 d17 1 d1 18 d18 2 d2 19 d19 20 d20 3 d3 21 d21 22 d22 4 d4 5 d5 23 d23 24 d24 6 d6 7 d7 25 d25 26 d26 8 d8 9 d9 27 d27 28 d28 29 d29 30 d30 31 d31 32 d32 33 d33 34 d34} sdmmc_data_oe {0 cdata_out_en0 4 cdata_out_en4 5 cdata_out_en5 1 cdata_out_en1 2 cdata_out_en2 6 cdata_out_en6 7 cdata_out_en7 3 cdata_out_en3} uart0_out1_n {0 out1_n} spim0_ss_in_n {0 ss_in_n} nand_rdy_busy_i {0 rdy_bsy_in0 1 rdy_bsy_in1 2 rdy_bsy_in2 3 rdy_bsy_in3} nand_adq_oe {0 adq_oe0} uart0_dtr_n {0 dtr_n} spim1_ss_in_n {0 ss_in_n} usb1_ulpi_dir {0 ulpi_dir} sdmmc_data_o {0 cdata_out0 4 cdata_out4 5 cdata_out5 1 cdata_out1 2 cdata_out2 6 cdata_out6 7 cdata_out7 3 cdata_out3} emac2_ptp_tstmp_data {0 ptp_tstmp_data} i2c_emac2_sda_i {0 ic_data_in_a} i2c_emac0_scl_i {0 ic_clk_in_a} emac2_ptp_tstmp_en {0 ptp_tstmp_en} emac0_gmii_mdi_i {0 mdi} usb1_ulpi_clk {0 ulpi_clk} nand_wp_o {0 wp_outn} emac2_rst_clk_rx_n_o {0 rst_clk_rx_n_o} emac2_phy_txd_o {0 txd0 4 txd4 5 txd5 1 txd1 2 txd2 6 txd6 7 txd7 3 txd3} i2c_emac1_sda_oe {0 ic_data_oe} i2c1_scl_i {0 ic_clk_in_a} emac0_phy_rxdv_i {0 rxdv} emac0_ptp_pps_o {0 ptp_pps} emac1_gmii_mdo_o {0 mdo} trace_clk_ctl {0 clk_ctl} nand_we_o {0 we_outn} emac1_ptp_tstmp_data {0 ptp_tstmp_data} uart1_out2_n {0 out2_n} emac1_phy_txen_o {0 txen} emac1_rst_clk_rx_n_o {0 rst_clk_rx_n_o} i2c_emac0_sda_oe {0 ic_data_oe} usb1_ulpi_data_i {0 ulpi_datain0 4 ulpi_datain4 5 ulpi_datain5 1 ulpi_datain1 2 ulpi_datain2 6 ulpi_datain6 7 ulpi_datain7 3 ulpi_datain3} nand_re_o {0 re_outn} trace_clkin {0 clkin} emac1_phy_txer_o {0 txer} uart1_tx {0 sout} usb1_ulpi_data_oe {0 ulpi_data_out_en0 4 ulpi_data_out_en4 5 ulpi_data_out_en5 1 ulpi_data_out_en1 2 ulpi_data_out_en2 6 ulpi_data_out_en6 7 ulpi_data_out_en7 3 ulpi_data_out_en3} emac2_phy_rxer_i {0 rxer} spim1_miso_i {0 rxd} emac0_ptp_tstmp_data {0 ptp_tstmp_data} uart1_rts_n {0 rts_n} uart0_out2_n {0 out2_n} sdmmc_wp_i {0 wp_i} emac0_clk_tx_i {0 tx_clk_i} i2c_emac1_sda_i {0 ic_data_in_a} spim0_mosi_oe {0 ssi_oe_n} usb1_ulpi_data_o {0 ulpi_dataout0 4 ulpi_dataout4 5 ulpi_dataout5 1 ulpi_dataout1 2 ulpi_dataout2 6 ulpi_dataout6 7 ulpi_dataout7 3 ulpi_dataout3} emac0_phy_col_i {0 col} emac0_rst_clk_rx_n_o {0 rst_clk_rx_n_o} spim1_mosi_oe {0 ssi_oe_n} emac0_phy_crs_i {0 crs} emac1_gmii_mdo_o_e {0 mdo_en} nand_ce_o {0 ce_outn0 1 ce_outn1 2 ce_outn2 3 ce_outn3} emac2_gmii_mdc_o {0 mdc} i2c0_scl_i {0 ic_clk_in_a} emac2_rst_clk_tx_n_o {0 rst_clk_tx_n_o}} MAINPLLGRP_GPIO_DB_CNT 1 MAINPLLGRP_VCO_DENOM 1 USB0_PinMuxing IO S2F_Width 3 TRACE_Mode N/A I2CEMAC2_PinMuxing Unused S2FINTERRUPT_I2C1_Enable false FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2CEMAC2_SCL_IN 100 S2FINTERRUPT_CLOCKPERIPHERAL_Enable false FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC0_RX_CLK_IN 100 IO_OUTPUT_DELAY10 0 DEFAULT_MPU_CLK 1000 H2F_COLD_RST_Enable false IO_OUTPUT_DELAY11 0 F2SDRAM2_Width 3 IO_OUTPUT_DELAY12 17 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC2_MD_CLK 2.5 MAINPLLGRP_EMACB_CNT 999 IO_OUTPUT_DELAY13 0 S2FINTERRUPT_I2CEMAC1_Enable false FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_GTX_CLK 125 MAINPLLGRP_EMAC_PTP_CNT 999 IO_OUTPUT_DELAY14 0 PERI_PLL_AUTO_VCO_FREQ 3000 IO_OUTPUT_DELAY15 0 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C0_SCL_IN 100 IO_OUTPUT_DELAY16 0 IO_OUTPUT_DELAY17 0 IO_OUTPUT_DELAY18 0 F2H_SDRAM1_CLOCK_FREQ 100 EMAC0_CLK 250 IO_OUTPUT_DELAY20 0 IO_OUTPUT_DELAY19 0 DMA_PeriphId_DERIVED {0 1 2 3 4 5 6 7} IO_OUTPUT_DELAY21 0 IO_OUTPUT_DELAY22 0 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2CEMAC0_SCL_IN 100 IO_OUTPUT_DELAY23 0 PERPLLGRP_NOC_CNT 2 IO_OUTPUT_DELAY24 0 IO_OUTPUT_DELAY25 0 IO_OUTPUT_DELAY26 0 IO_OUTPUT_DELAY27 0 F2SDRAM1_Width 3 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_MD_CLK 2.5 IO_OUTPUT_DELAY28 0 DMA_Enable {No No No No No No No No} FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC1_TX_CLK_IN 100 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C1_CLK 100 IO_OUTPUT_DELAY30 0 IO_OUTPUT_DELAY29 0 EMAC1_PTP false IO_OUTPUT_DELAY31 0 eosc1_clk_mhz 25.0 PSI_CLK_FREQ 500 IO_OUTPUT_DELAY32 0 IO_OUTPUT_DELAY33 0 IO_OUTPUT_DELAY34 0 PERPLLGRP_MPU_CNT 999 IO_OUTPUT_DELAY35 0 IO_OUTPUT_DELAY36 0 IO_OUTPUT_DELAY37 0 IO_OUTPUT_DELAY38 0 IO_OUTPUT_DELAY40 0 IO_OUTPUT_DELAY39 0 IO_OUTPUT_DELAY41 0 IO_OUTPUT_DELAY42 0 S2FINTERRUPT_GPIO_Enable false H2F_USER0_CLK_FREQ 500 IO_OUTPUT_DELAY43 0 H2F_USER0_CLK_Enable false MAINPLLGRP_PSI_CNT 999 IO_OUTPUT_DELAY44 0 F2SDRAM0_Width 3 quartus_ini_hps_ip_enable_s10_advanced_options false IO_OUTPUT_DELAY45 0 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC2_RX_CLK_IN 100 UART0_Mode No_flow_control IO_OUTPUT_DELAY46 0 F2H_SDRAM2_CLOCK_FREQ 100 IO_OUTPUT_DELAY47 0 NOCDIV_L4MPCLK 1 H2F_PENDING_RST_Enable false F2SDRAM1_ready_latency 0 I2C0_PinMuxing Unused S2FINTERRUPT_SPIS1_Enable false S2FINTERRUPT_SPIM0_Enable false FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2CEMAC1_CLK 100 USB1_Mode N/A S2FINTERRUPT_DMA_Enable false H2F_CTI_CLOCK_FREQ 100 SPIM1_PinMuxing Unused CLK_EMACB_SOURCE 1 SPIS0_Mode N/A MAINPLLGRP_VCO_NUMER 74 EMAC0_PinMuxing IO SPIS0_PinMuxing Unused PERPLLGRP_S2F_USER1_CNT 1 CM_PinMuxing Unused SPIM1_Mode N/A F2S_ADDRESS_WIDTH 32 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC_PTP_REF_CLOCK 100000000 PERPLLGRP_SDMMC_CNT 999 S2FINTERRUPT_UART0_Enable false TESTIOCTRL_PERICLKSEL 8 pin_muxing_check {} S2FINTERRUPT_SYSTIMER_Enable false S2FINTERRUPT_EMAC2_Enable false H2F_USER1_CLK_Enable false RUN_INTERNAL_BUILD_CHECKS 0 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_USB0_CLK_IN 100 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SPIS0_SCLK_IN 100 I2CEMAC1_Mode N/A F2H_AXI_CLOCK_FREQ 100000000 F2H_SDRAM3_CLOCK_FREQ 100 CLK_NOC_SOURCE 0 TESTIOCTRL_DEBUGCLKSEL 16 MPU_CLK_VCCL 2 EMAC1_Mode RGMII_with_MDIO USE_DEFAULT_MPU_CLK false GP_Enable false eosc1_clk_hz 0 IO_INPUT_DELAY10 0 IO_INPUT_DELAY11 0 S2F_ADDRESS_WIDTH 32 IO_INPUT_DELAY12 0 IO_INPUT_DELAY13 0 IO_INPUT_DELAY14 0 IO_INPUT_DELAY15 0 S2FINTERRUPT_EMAC0_Enable false FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC2_GTX_CLK 125 IO_INPUT_DELAY16 0 IO_INPUT_DELAY17 0 MAINPLLGRP_PERIPH_REF_CNT 999 IO_INPUT_DELAY18 0 NAND_PinMuxing Unused IO_INPUT_DELAY20 0 IO_INPUT_DELAY19 0 IO_INPUT_DELAY21 0 IO_INPUT_DELAY22 0 EMAC2_CLK 250 IO_INPUT_DELAY23 0 IO_INPUT_DELAY24 0 IO_INPUT_DELAY25 0 GPIO_REF_CLK 4 OVERIDE_PERI_PLL false PERPLLGRP_EMAC_PTP_CNT 9 IO_INPUT_DELAY26 0 EMAC2_PinMuxing FPGA IO_INPUT_DELAY27 0 IO_INPUT_DELAY28 0 LWH2F_ADDRESS_WIDTH 21 DEBUG_APB_Enable false EMIF_BYPASS_CHECK false IO_INPUT_DELAY30 0 IO_INPUT_DELAY29 0 F2H_FREE_CLK_Enable false IO_INPUT_DELAY31 0 PERPLLGRP_VCO_DENOM 1 IO_INPUT_DELAY32 0 F2H_SDRAM4_CLOCK_FREQ 100 IO_INPUT_DELAY33 0 IO_INPUT_DELAY34 0 F2SDRAM2_ready_latency 0 EMAC2SEL 0 IO_INPUT_DELAY35 0 IO_INPUT_DELAY36 0 CTI_Enable false W_RESET_ACTION 0 IO_INPUT_DELAY37 0 PERPLLGRP_PSI_CNT 1 IO_INPUT_DELAY38 0 IO_INPUT_DELAY40 0 IO_INPUT_DELAY39 0 SDMMC_REF_CLK 200 IO_INPUT_DELAY41 0 IO_INPUT_DELAY42 0 H2F_LW_AXI_CLOCK_FREQ 125000000 PERPLLGRP_EMACB_CNT 999 IO_INPUT_DELAY43 0 IO_INPUT_DELAY44 0 IO_INPUT_DELAY45 0 GPIO_REF_CLK2 200 IO_INPUT_DELAY46 0 F2H_FREE_CLK_FREQ 200 IO_INPUT_DELAY47 0 MAINPLLGRP_EMACA_CNT 999 H2F_USER1_CLK_FREQ 500 L4_SYS_FREE_CLK 1 quartus_ini_hps_ip_l2_at_12000 false LWH2F_Enable 1 I2CEMAC1_PinMuxing Unused F2H_SDRAM5_CLOCK_FREQ 100 CLK_S2F_USER1_SOURCE 1 TEST_Enable false NOCDIV_CS_PDBGCLK 1 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C0_CLK 100 PERPLLGRP_GPIO_DB_CNT 999 NOCDIV_CS_TRACECLK 0 HPS_DIV_GPIO_FREQ 125 CLK_GPIO_SOURCE 0 EMAC0_PTP false NOCDIV_L4MAINCLK 0 I2C1_Mode default S2FINTERRUPT_SYSTEMMANAGER_Enable false S2FINTERRUPT_USB0_Enable false PIN_TO_BALL_MAP {35 A32 36 P30 37 J30 38 A31 40 D31 39 H30 41 H32 42 B29 43 J31 44 D33 45 D28 46 K31 47 B28 10 B30 11 D29 12 F31 13 R29 14 G28 15 F30 16 J28 0 E29 17 E28 1 C33 18 B34 2 D30 19 E31 20 P29 3 A30 21 B32 4 C32 22 G29 5 A27 23 H28 6 A29 24 G30 7 E33 25 C28 8 F29 26 F32 9 E32 27 K29 28 A34 29 N30 30 B33 31 H31 32 K28 33 J29 34 G32} HPS_IO_Enable {USB0:CLK USB0:STP USB0:DIR USB0:DATA0 USB0:DATA1 USB0:NXT USB0:DATA2 USB0:DATA3 USB0:DATA4 USB0:DATA5 USB0:DATA6 USB0:DATA7 EMAC0:TX_CLK EMAC0:TX_CTL EMAC0:RX_CLK EMAC0:RX_CTL EMAC0:TXD0 EMAC0:TXD1 EMAC0:RXD0 EMAC0:RXD1 EMAC0:TXD2 EMAC0:TXD3 EMAC0:RXD2 EMAC0:RXD3 GPIO GPIO UART0:TX UART0:RX GPIO GPIO I2C1:SDA I2C1:SCL JTAG:TCK JTAG:TMS JTAG:TDO JTAG:TDI SDMMC:D0 SDMMC:CMD SDMMC:CCLK SDMMC:D1 SDMMC:D2 SDMMC:D3 HPS_OSC_CLK GPIO GPIO GPIO MDIO0:MDIO MDIO0:MDC} S2FINTERRUPT_SDMMC_Enable false FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SPIS1_SCLK_IN 100 UART1_PinMuxing Unused S2FINTERRUPT_I2CEMAC2_Enable false F2SDRAM_ADDRESS_WIDTH 32 EMAC1SEL 0 TRACE_PinMuxing Unused FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C1_SCL_IN 100 USB0_Mode default FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC0_TX_CLK_IN 100 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SDMMC_CCLK 100 DISABLE_PERI_PLL false CLK_PERI_PLL_SOURCE2 0 S2FINTERRUPT_I2C0_Enable false FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2CEMAC1_SCL_IN 100 EMIF_CONDUIT_Enable true SPIM0_Mode N/A FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2CEMAC0_CLK 100 PERPLLGRP_VCO_NUMER 74 S2FINTERRUPT_L4TIMER_Enable false H2F_TPIU_CLOCK_IN_FREQ 100 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_MD_CLK 2.5 USB1_PinMuxing Unused S2FINTERRUPT_I2CEMAC0_Enable false PERPLLGRP_S2F_USER0_CNT 1 EMAC0_SWITCH_Enable false S2FINTERRUPT_WATCHDOG_Enable false FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC1_RX_CLK_IN 100 I2CEMAC0_Mode N/A EMAC0_Mode RGMII_with_MDIO MAINPLLGRP_S2F_USER1_CNT 999 pin_muxing {} INTERNAL_OSCILLATOR_ENABLE 60 IO_OUTPUT_DELAY0 0 SPIM0_PinMuxing Unused IO_OUTPUT_DELAY1 0 PERI_PLL_MANUAL_VCO_FREQ 2000 IO_OUTPUT_DELAY2 0 IO_OUTPUT_DELAY3 0 IO_OUTPUT_DELAY4 0 IO_OUTPUT_DELAY5 0 IO_OUTPUT_DELAY6 0 IO_OUTPUT_DELAY7 0 CUSTOM_MPU_CLK 800 L3_MAIN_FREE_CLK 400 IO_INPUT_DELAY0 0 IO_OUTPUT_DELAY8 0 F2SINTERRUPT_Enable true IO_INPUT_DELAY1 0 IO_OUTPUT_DELAY9 0 S2FINTERRUPT_SPIM1_Enable false IO_INPUT_DELAY2 0 device_name 1SX280LU2F50E2VG IO_INPUT_DELAY3 0 IO_INPUT_DELAY4 0 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC2_TX_CLK_IN 100 IO_INPUT_DELAY5 0 HPS_DIV_GPIO_FREQ2 200 EMAC0SEL 0 IO_INPUT_DELAY6 0 IO_INPUT_DELAY7 0 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM0_SCLK_OUT 100 IO_INPUT_DELAY8 0 CLK_PSI_SOURCE 1 IO_INPUT_DELAY9 0 CONFIG_HPS_DIV_GPIO 1 EMAC1_CLK 250 S2FINTERRUPT_UART1_Enable false watchdog_reset true MPU_EVENTS_Enable false S2FINTERRUPT_SPIS0_Enable false EMAC_PTP_REF_CLK 100 CLK_EMACA_SOURCE 1 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_USB1_CLK_IN 100 hps_device_family {Stratix 10} EMAC2_PTP false CLK_MPU_SOURCE 0 I2C1_PinMuxing IO NAND_Mode N/A PERPLLGRP_EMACA_CNT 3 S2FINTERRUPT_EMAC1_Enable false EMAC1_PinMuxing FPGA SPIS1_PinMuxing Unused EMAC1_SWITCH_Enable false HPS_BOOT 1 F2S_ready_latency 0 PLL_CLK0 Unused FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_GTX_CLK 100 PLL_CLK1 Unused quartus_ini_hps_ip_enable_test_interface false PLL_CLK2 Unused quartus_ini_hps_ip_enable_ace_interface false PLL_CLK3 Unused CM_Mode N/A PLL_CLK4 Unused FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2CEMAC2_CLK 100 CLK_MAIN_PLL_SOURCE2 0 TESTIOCTRL_MAINCLKSEL 8 UART1_Mode N/A I2C0_Mode N/A STM_Enable true S2F_ready_latency 0
generateLegacySim false
  

Software Assignments

(none)

altera_stratix10_hps_inst_clk_0

hps_clk_src v19.1


Parameters

deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

altera_stratix10_hps_inst_bridges

stratix10_hps_bridge_avalon v19.1
altera_stratix10_hps_inst_clk_0 clk   altera_stratix10_hps_inst_bridges
  clock_sink
clk_reset  
  reset_sink


Parameters

address_map
F2S_mode 0
F2S_Width 3
F2S_ready_latency 0
S2F_Width 3
S2F_ready_latency 0
LWH2F_Enable 1
LWH2F_ready_latency 0
F2SDRAM0_Width 3
F2SDRAM0_ready_latency 0
F2SDRAM1_Width 3
F2SDRAM1_ready_latency 0
F2SDRAM2_Width 3
F2SDRAM2_ready_latency 0
F2SDRAM_ADDRESS_WIDTH 32
F2S_ADDRESS_WIDTH 32
S2F_ADDRESS_WIDTH 32
LWH2F_ADDRESS_WIDTH 21
quartus_ini_hps_ip_enable_ace_interface false
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

altera_stratix10_hps_inst_eosc1

hps_virt_clk v19.1


Parameters

clockFrequency 25000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

altera_stratix10_hps_inst_cb_intosc_hs_div2_clk

hps_virt_clk v19.1


Parameters

clockFrequency 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

altera_stratix10_hps_inst_cb_intosc_ls_clk

hps_virt_clk v19.1


Parameters

clockFrequency 60000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

altera_stratix10_hps_inst_f2s_free_clk

hps_virt_clk v19.1


Parameters

clockFrequency 200000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

altera_stratix10_hps_inst_arm_a9_0

arm_a9 v19.1
altera_stratix10_hps_inst_clk_0 clk   altera_stratix10_hps_inst_arm_a9_0
  clock_sink
clk_reset  
  reset_sink
altera_axi_master   altera_stratix10_hps_inst_arm_gic_0
  axi_slave0
altera_axi_master  
  axi_slave1


Parameters

address_map <address-map><slave name='arm_gic_0.axi_slave1' start='0xFFFFC100' end='0xFFFFC200' datawidth='32' /><slave name='arm_gic_0.axi_slave0' start='0xFFFFD000' end='0xFFFFE000' datawidth='32' /></address-map>
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

altera_stratix10_hps_inst_arm_a9_1

arm_a9 v19.1
altera_stratix10_hps_inst_clk_0 clk   altera_stratix10_hps_inst_arm_a9_1
  clock_sink
clk_reset  
  reset_sink
altera_axi_master   altera_stratix10_hps_inst_arm_gic_0
  axi_slave0
altera_axi_master  
  axi_slave1


Parameters

address_map <address-map><slave name='arm_gic_0.axi_slave1' start='0xFFFFC100' end='0xFFFFC200' datawidth='32' /><slave name='arm_gic_0.axi_slave0' start='0xFFFFD000' end='0xFFFFE000' datawidth='32' /></address-map>
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

altera_stratix10_hps_inst_arm_gic_0

stratix10_arm_gic v19.1
altera_stratix10_hps_inst_clk_0 clk   altera_stratix10_hps_inst_arm_gic_0
  clock_sink
clk_reset  
  reset_sink
altera_stratix10_hps_inst_arm_a9_0 altera_axi_master  
  axi_slave0
altera_axi_master  
  axi_slave1
altera_stratix10_hps_inst_arm_a9_1 altera_axi_master  
  axi_slave0
altera_axi_master  
  axi_slave1


Parameters

deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)
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