xcvr_fpll_1G

2019.06.28.18:30:50 Datasheet
Overview

Memory Map

altera_xcvr_fpll_s10_htile_inst

altera_xcvr_fpll_s10_htile v19.1


Parameters

rcfg_enable 0
rcfg_jtag_enable 0
rcfg_separate_avmm_busy 0
set_capability_reg_enable 0
set_user_identifier 0
set_csr_soft_logic_enable 0
rcfg_file_prefix altera_xcvr_fpll_s10
rcfg_sv_file_enable 0
rcfg_h_file_enable 0
rcfg_mif_file_enable 0
rcfg_multi_enable 0
set_rcfg_emb_strm_enable 0
rcfg_reduced_files_enable 0
rcfg_profile_cnt 2
rcfg_profile_select 1
rcfg_profile_data0
rcfg_profile_data1
rcfg_profile_data2
rcfg_profile_data3
rcfg_profile_data4
rcfg_profile_data5
rcfg_profile_data6
rcfg_profile_data7
generate_docs 1
set_primary_use 2
message_level error
set_prot_mode 0
set_bw_sel low
set_refclk_cnt 1
set_refclk_index 0
set_output_clock_frequency 625.0
output_datarate 1250.0
set_enable_fractional 0
set_auto_reference_clock_frequency 125.0
select_manual_config false
set_m_counter 40
set_ref_clk_div 1
set_l_counter 8
set_power_mode 1_0V
enable_mcgb 1
mcgb_div 1
enable_hfreq_clk 1
enable_mcgb_pcie_clksw 0
enable_mcgb_reset 0
mcgb_aux_clkin_cnt 0
mcgb_in_clk_freq 625.0
mcgb_out_datarate 1250.0
enable_bonding_clks 0
pma_width 64
set_parameter_list L-Counter,M-Counter,N-Counter,C-Counter,K-Counter,PLL output datarate,PLL output frequency,VCO frequency,PFD frequency,C0 Counter Output Frequency,C0 Counter Output Frequency in Hz,C1 Counter Output Frequency,C1 Counter Output Frequency in Hz
set_parameter_values 8,40,1,1,0,1250.0,625.0,10000.0,125.0,0,0,0,0
set_display_units ,,,,,Mbps,MHz,MHz,MHz,ps,ps,ps,ps
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)
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