interface_type_hwtcl |
Avalon-MM |
app_interface_width_hwtcl |
256-bit |
app_interface_freq_hwtcl |
250 MHz |
wrala_hwtcl |
Gen3x8, Interface - 256 bit, 250 MHz |
select_design_example_hwtcl |
PIO |
virtual_rp_ep_mode_hwtcl |
Root Port |
pf0_bar0_type_gui_hwtcl |
64-bit prefetchable memory |
pf0_bar0_address_width_mask_hwtcl |
28 |
pf0_bar0_enable_rxm_burst_hwtcl |
0 |
pf0_bar1_type_hwtcl |
Disabled |
pf0_bar1_address_width_mask_hwtcl |
28 |
pf0_bar1_enable_rxm_burst_hwtcl |
0 |
pf0_bar2_type_hwtcl |
Disabled |
pf0_bar2_address_width_mask_hwtcl |
28 |
pf0_bar2_enable_rxm_burst_hwtcl |
0 |
pf0_bar3_type_hwtcl |
Disabled |
pf0_bar3_address_width_mask_hwtcl |
28 |
pf0_bar3_enable_rxm_burst_hwtcl |
0 |
pf0_bar4_type_hwtcl |
Disabled |
pf0_bar4_address_width_mask_hwtcl |
28 |
pf0_bar4_enable_rxm_burst_hwtcl |
0 |
pf0_bar5_type_hwtcl |
Disabled |
pf0_bar5_address_width_mask_hwtcl |
28 |
pf0_bar5_enable_rxm_burst_hwtcl |
0 |
avmm_addr_width_hwtcl |
32 |
dma_enabled_hwtcl |
0 |
enable_cra_slave_port_hwtcl |
1 |
enable_advanced_interrupt_hwtcl |
0 |
enable_hip_status_for_avmm_hwtcl |
1 |
txs_enabled_hwtcl |
0 |
hptxs_enabled_hwtcl |
1 |
hptxs_enabled_mapping_hwtcl |
1 |
hptxs_address_translation_table_address_width_hwtcl |
1 |
hptxs_address_translation_window_address_width_hwtcl |
27 |
cg_a2p_addr_map_num_entries_hwtcl |
2 |
cg_a2p_addr_map_pass_thru_bits_hwtcl |
12 |
virtual_maxpayload_size_hwtcl |
512 |
pf0_pcie_cap_port_num_hwtcl |
1 |
pf0_pcie_cap_slot_clk_config_hwtcl |
1 |
pf0_pci_msi_multiple_msg_cap_hwtcl |
4 |
virtual_pf0_msix_enable_hwtcl |
0 |
pf0_pci_msix_table_size_hwtcl |
0 |
pf0_pci_msix_table_offset_hwtcl |
0 |
pf0_pci_msix_bir_hwtcl |
0 |
pf0_pci_msix_pba_offset_hwtcl |
0 |
pf0_pci_msix_pba_hwtcl |
0 |
pf0_pcie_slot_imp_hwtcl |
0 |
pf0_pcie_cap_slot_power_limit_value_hwtcl |
0 |
pf0_pcie_cap_slot_power_limit_scale_hwtcl |
0 |
pf0_pcie_cap_phy_slot_num_hwtcl |
0 |
pf0_pcie_cap_ep_l0s_accpt_latency_hwtcl |
0 |
pf0_pcie_cap_ep_l1_accpt_latency_hwtcl |
0 |
cvp_user_id_hwtcl |
0 |
hip_reconfig_hwtcl |
1 |
xcvr_reconfig_hwtcl |
0 |
xcvr_adme_hwtcl |
0 |
pcie_link_inspector_hwtcl |
0 |
anlg_voltage |
1_0V |
pf0_pci_type0_vendor_id_hwtcl |
4466 |
pf0_pci_type0_device_id_hwtcl |
57344 |
pf0_revision_id_hwtcl |
1 |
pf0_class_code_hwtcl |
394240 |
pf0_subsys_vendor_id_hwtcl |
4466 |
pf0_subsys_dev_id_hwtcl |
57344 |
enable_example_design_sim_rp_hwtcl |
0 |
enable_example_design_synth_rp_hwtcl |
0 |
select_design_example_rtl_lang_hwtcl |
Verilog |
chosen_devkit_hwtcl |
NONE |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |