---

ILC

interrupt_latency_counter v19.1

Parameters generateLegacySim false

  

Software Assignments (none)

---

a10_hps

altera_arria10_hps v19.1

Parameters MPU_EVENTS_Enable false GP_Enable false DEBUG_APB_Enable false STM_Enable true CTI_Enable false BOOT_FROM_FPGA_Enable false BSEL_EN false BSEL 1 F2S_Width 6 S2F_Width 4 LWH2F_Enable 2 F2SDRAM_PORT_CONFIG 6 F2SDRAM0_ENABLED true F2SDRAM1_ENABLED false F2SDRAM2_ENABLED true F2SDRAM_READY_LATENCY true F2SDRAM_ADDRESS_WIDTH 32 DMA_PeriphId_DERIVED 0,1,2,3,4,5,6,7 DMA_Enable No,No,No,No,No,No,No,No SECURITY_MODULE_Enable false EMAC0_SWITCH_Enable false EMAC1_SWITCH_Enable false EMAC2_SWITCH_Enable false F2SINTERRUPT_Enable true S2FINTERRUPT_CLOCKPERIPHERAL_Enable false S2FINTERRUPT_CTI_Enable false S2FINTERRUPT_DMA_Enable false S2FINTERRUPT_EMAC0_Enable false S2FINTERRUPT_EMAC1_Enable false S2FINTERRUPT_EMAC2_Enable false S2FINTERRUPT_FPGAMANAGER_Enable false S2FINTERRUPT_GPIO_Enable false S2FINTERRUPT_HMC_Enable false S2FINTERRUPT_I2CEMAC0_Enable false S2FINTERRUPT_I2CEMAC1_Enable false S2FINTERRUPT_I2CEMAC2_Enable false S2FINTERRUPT_I2C0_Enable false S2FINTERRUPT_I2C1_Enable false S2FINTERRUPT_L4TIMER_Enable false S2FINTERRUPT_NAND_Enable false S2FINTERRUPT_QSPI_Enable false S2FINTERRUPT_SYSTIMER_Enable false S2FINTERRUPT_SDMMC_Enable false S2FINTERRUPT_SPIM0_Enable false S2FINTERRUPT_SPIM1_Enable false S2FINTERRUPT_SPIS0_Enable false S2FINTERRUPT_SPIS1_Enable false S2FINTERRUPT_SYSTEMMANAGER_Enable false S2FINTERRUPT_UART0_Enable false S2FINTERRUPT_UART1_Enable false S2FINTERRUPT_USB0_Enable false S2FINTERRUPT_USB1_Enable false S2FINTERRUPT_WATCHDOG_Enable false eosc1_clk_mhz 25.0 F2H_FREE_CLK_Enable false F2H_FREE_CLK_FREQ 200 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_MD_CLK 2.5 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_GTX_CLK 100 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_MD_CLK 2.5 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_GTX_CLK 125 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC2_MD_CLK 2.5 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC2_GTX_CLK 125 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_QSPI_SCLK_OUT 100 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SDMMC_CCLK 100 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM0_SCLK_OUT 100 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM1_SCLK_OUT 100 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C0_CLK 100 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C1_CLK 100 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2CEMAC0_CLK 100 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2CEMAC1_CLK 100 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2CEMAC2_CLK 100 DEFAULT_MPU_CLK 1200 MPU_CLK_VCCL 1 USE_DEFAULT_MPU_CLK false CUSTOM_MPU_CLK 1020 H2F_USER0_CLK_Enable false H2F_USER0_CLK_FREQ 400 H2F_USER1_CLK_Enable false H2F_USER1_CLK_FREQ 400 SDMMC_REF_CLK 200 L3_MAIN_FREE_CLK 200 L4_SYS_FREE_CLK 1 NOCDIV_L4MAINCLK 0 NOCDIV_L4MPCLK 0 NOCDIV_L4SPCLK 2 NOCDIV_CS_ATCLK 0 NOCDIV_CS_PDBGCLK 1 NOCDIV_CS_TRACECLK 1 HPS_DIV_GPIO_FREQ 125 EMAC0_CLK 250 EMAC1_CLK 250 EMAC2_CLK 250 CLK_MAIN_PLL_SOURCE2 0 CLK_PERI_PLL_SOURCE2 0 CLK_S2F_USER0_SOURCE 0 CLK_S2F_USER1_SOURCE 0 CLK_EMAC_PTP_SOURCE 1 CLK_GPIO_SOURCE 1 CLK_SDMMC_SOURCE 1 CLK_EMACA_SOURCE 1 CLK_EMACB_SOURCE 1 H2F_PENDING_RST_Enable false H2F_COLD_RST_Enable false F2H_DBG_RST_Enable true F2H_WARM_RST_Enable true F2H_COLD_RST_Enable true EMIF_CONDUIT_Enable true EMAC0_PTP false EMAC1_PTP false EMAC2_PTP false deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

a10_hps_fpga_interfaces

altera_arria10_interface_generator v14.0

Parameters interfaceDefinition constraints {} instances {interrupts {signal_widths {} parameters {} location HPSINTERFACEINTERRUPTS_X78_Y180_N96 entity_name twentynm_hps_interface_interrupts signal_default_terminations {} signal_terminations {}} boot_from_fpga {signal_widths {f2s_bsel 3 f2s_boot_from_fpga_on_failure 1 f2s_bsel_en 1 f2s_boot_from_fpga_ready 1} parameters {} location HPSINTERFACEBOOTFROMFPGA_X79_Y172_N96 entity_name twentynm_hps_interface_boot_from_fpga signal_default_terminations {f2s_bsel 0 f2s_boot_from_fpga_on_failure 0 f2s_bsel_en 0 f2s_boot_from_fpga_ready 0} signal_terminations {f2s_bsel {2:0 1} f2s_boot_from_fpga_on_failure {0:0 0} f2s_bsel_en {0:0 0} f2s_boot_from_fpga_ready {0:0 0}}} clocks_resets {signal_widths {f2s_free_clk 1 f2s_pending_rst_ack 1} parameters {} location HPSINTERFACECLOCKSRESETS_X78_Y168_N96 entity_name twentynm_hps_interface_clocks_resets signal_default_terminations {f2s_free_clk 1 f2s_pending_rst_ack 1} signal_terminations {f2s_free_clk {0:0 0} f2s_pending_rst_ack {0:0 1}}} emif_interface {signal_widths {} parameters {} location HPSINTERFACEDDR_X78_Y171_N96 entity_name a10_hps_emif_interface signal_default_terminations {} signal_terminations {}} stm_event {signal_widths {} parameters {} location HPSINTERFACESTMEVENT_X78_Y204_N96 entity_name twentynm_hps_interface_stm_event signal_default_terminations {} signal_terminations {}} debug_apb {signal_widths {F2S_PCLKENDBG 1 F2S_DBGAPB_DISABLE 1} parameters {} location HPSINTERFACEDBGAPB_X78_Y170_N96 entity_name twentynm_hps_interface_dbg_apb signal_default_terminations {F2S_PCLKENDBG 0 F2S_DBGAPB_DISABLE 0} signal_terminations {F2S_PCLKENDBG {0:0 0} F2S_DBGAPB_DISABLE {0:0 0}}} @orderednames {clocks_resets debug_apb stm_event boot_from_fpga emif_interface interrupts}} interfaces {@orderednames {h2f_reset f2h_cold_reset_req f2h_debug_reset_req f2h_warm_reset_req f2h_stm_hw_events emif} h2f_reset {properties {associatedResetSinks {f2h_warm_reset_req f2h_cold_reset_req} synchronousEdges none} direction Output type reset signals {@orderednames h2f_rst_n h2f_rst_n {width 1 properties {} instance_name clocks_resets internal_name s2f_user3_clk direction Output role reset_n fragments {}}}} f2h_cold_reset_req {properties {synchronousEdges none} direction Input type reset signals {@orderednames f2h_cold_rst_req_n f2h_cold_rst_req_n {width 1 properties {} instance_name clocks_resets internal_name f2s_cold_rst_req_n direction Input role reset_n fragments {}}}} f2h_debug_reset_req {properties {synchronousEdges none} direction Input type reset signals {@orderednames f2h_dbg_rst_req_n f2h_dbg_rst_req_n {width 1 properties {} instance_name clocks_resets internal_name f2s_dbg_rst_req_n direction Input role reset_n fragments {}}}} f2h_warm_reset_req {properties {synchronousEdges none} direction Input type reset signals {@orderednames f2h_warm_rst_req_n f2h_warm_rst_req_n {width 1 properties {} instance_name clocks_resets internal_name f2s_warm_rst_req_n direction Input role reset_n fragments {}}}} f2h_stm_hw_events {properties {} direction Input type conduit signals {@orderednames f2h_stm_hwevents f2h_stm_hwevents {width 28 properties {} instance_name stm_event internal_name f2s_stm_event direction Input role stm_hwevents fragments {}}}} emif {properties {} direction Output type conduit signals {@orderednames {emif_emif_to_hps emif_hps_to_emif emif_emif_to_gp emif_gp_to_emif} emif_emif_to_hps {width 4096 properties {} instance_name emif_interface internal_name emif_to_hps direction Input role emif_to_hps fragments {}} emif_hps_to_emif {width 4096 properties {} instance_name emif_interface internal_name hps_to_emif direction Output role hps_to_emif fragments {}} emif_emif_to_gp {width 1 properties {} instance_name emif internal_name emif_emif_to_gp direction Input role emif_to_gp fragments {}} emif_gp_to_emif {width 2 properties {} instance_name emif internal_name emif_gp_to_emif direction Output role gp_to_emif fragments {}}}}} properties {} interface_sim_style {} raw_assigns {} intermediate_wire_count 0 raw_assign_sim_style {} wires_to_fragments {} wire_sim_style {} qipEntries ignoreSimulation false hps_parameter_map deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

a10_hps_hps_io

altera_arria10_hps_io v19.1

Parameters border_description constraints {} instances {phery_uart1 {signal_widths {} parameters {} location HPSPERIPHERALUART_X79_Y169_N96 entity_name twentynm_hps_peripheral_uart signal_default_terminations {} signal_terminations {}} phery_qspi {signal_widths {} parameters {} location HPSPERIPHERALQSPI_X78_Y218_N96 entity_name twentynm_hps_peripheral_qspi signal_default_terminations {} signal_terminations {}} phery_spim1 {signal_widths {} parameters {} location HPSPERIPHERALSPIMASTER_X78_Y221_N96 entity_name twentynm_hps_peripheral_spi_master signal_default_terminations {} signal_terminations {}} phery_usb0 {signal_widths {} parameters {} location HPSPERIPHERALUSB_X79_Y170_N96 entity_name twentynm_hps_peripheral_usb signal_default_terminations {} signal_terminations {}} phery_emac0 {signal_widths {} parameters {} location HPSPERIPHERALEMAC_X78_Y207_N96 entity_name twentynm_hps_peripheral_emac signal_default_terminations {} signal_terminations {}} @orderednames {phery_emac0 phery_qspi phery_usb0 phery_spim1 phery_trace phery_uart1 phery_i2c1 gpio} phery_i2c1 {signal_widths {} parameters {} location HPSPERIPHERALI2C_X78_Y212_N96 entity_name twentynm_hps_peripheral_i2c signal_default_terminations {} signal_terminations {}} phery_trace {signal_widths {} parameters {} location HPSPERIPHERALTPIUTRACE_X79_Y173_N96 entity_name twentynm_hps_peripheral_tpiu_trace signal_default_terminations {} signal_terminations {}} gpio {signal_widths {} parameters {} location HPSPERIPHERALGPIO_X78_Y210_N96 entity_name twentynm_hps_peripheral_gpio signal_default_terminations {} signal_terminations {}}} interfaces {@orderednames hps_io hps_io {properties {} direction input type conduit signals {@orderednames {hps_io_phery_emac0_TX_CLK hps_io_phery_emac0_TXD0 hps_io_phery_emac0_TXD1 hps_io_phery_emac0_TXD2 hps_io_phery_emac0_TXD3 hps_io_phery_emac0_RX_CTL hps_io_phery_emac0_TX_CTL hps_io_phery_emac0_RX_CLK hps_io_phery_emac0_RXD0 hps_io_phery_emac0_RXD1 hps_io_phery_emac0_RXD2 hps_io_phery_emac0_RXD3 hps_io_phery_emac0_MDIO hps_io_phery_emac0_MDC hps_io_phery_qspi_IO0 hps_io_phery_qspi_IO1 hps_io_phery_qspi_IO2_WPN hps_io_phery_qspi_IO3_HOLD hps_io_phery_qspi_CLK hps_io_phery_qspi_SS0 hps_io_phery_usb0_DATA0 hps_io_phery_usb0_DATA1 hps_io_phery_usb0_DATA2 hps_io_phery_usb0_DATA3 hps_io_phery_usb0_DATA4 hps_io_phery_usb0_DATA5 hps_io_phery_usb0_DATA6 hps_io_phery_usb0_DATA7 hps_io_phery_usb0_CLK hps_io_phery_usb0_STP hps_io_phery_usb0_DIR hps_io_phery_usb0_NXT hps_io_phery_spim1_CLK hps_io_phery_spim1_MOSI hps_io_phery_spim1_MISO hps_io_phery_spim1_SS0_N hps_io_phery_spim1_SS1_N hps_io_phery_trace_CLK hps_io_phery_trace_D0 hps_io_phery_trace_D1 hps_io_phery_trace_D2 hps_io_phery_trace_D3 hps_io_phery_uart1_RX hps_io_phery_uart1_TX hps_io_phery_i2c1_SDA hps_io_phery_i2c1_SCL hps_io_gpio_gpio1_io5 hps_io_gpio_gpio1_io14 hps_io_gpio_gpio1_io16 hps_io_gpio_gpio1_io17} hps_io_phery_emac0_TX_CLK {width 1 properties {} instance_name hps_io internal_name hps_io_phery_emac0_TX_CLK direction output role hps_io_phery_emac0_TX_CLK fragments phery_emac0:EMAC_CLK_TX(0:0)} hps_io_phery_emac0_TXD0 {width 1 properties {} instance_name hps_io internal_name hps_io_phery_emac0_TXD0 direction output role hps_io_phery_emac0_TXD0 fragments phery_emac0:EMAC_PHY_TXD(0:0)} hps_io_phery_emac0_TXD1 {width 1 properties {} instance_name hps_io internal_name hps_io_phery_emac0_TXD1 direction output role hps_io_phery_emac0_TXD1 fragments phery_emac0:EMAC_PHY_TXD(1:1)} hps_io_phery_emac0_TXD2 {width 1 properties {} instance_name hps_io internal_name hps_io_phery_emac0_TXD2 direction output role hps_io_phery_emac0_TXD2 fragments phery_emac0:EMAC_PHY_TXD(2:2)} hps_io_phery_emac0_TXD3 {width 1 properties {} instance_name hps_io internal_name hps_io_phery_emac0_TXD3 direction output role hps_io_phery_emac0_TXD3 fragments phery_emac0:EMAC_PHY_TXD(3:3)} hps_io_phery_emac0_RX_CTL {width 1 properties {} instance_name hps_io internal_name hps_io_phery_emac0_RX_CTL direction input role hps_io_phery_emac0_RX_CTL fragments phery_emac0:EMAC_PHY_RXDV(0:0)} hps_io_phery_emac0_TX_CTL {width 1 properties {} instance_name hps_io internal_name hps_io_phery_emac0_TX_CTL direction output role hps_io_phery_emac0_TX_CTL fragments phery_emac0:EMAC_PHY_TX_OE(0:0)} hps_io_phery_emac0_RX_CLK {width 1 properties {} instance_name hps_io internal_name hps_io_phery_emac0_RX_CLK direction input role hps_io_phery_emac0_RX_CLK fragments phery_emac0:EMAC_CLK_RX(0:0)} hps_io_phery_emac0_RXD0 {width 1 properties {} instance_name hps_io internal_name hps_io_phery_emac0_RXD0 direction input role hps_io_phery_emac0_RXD0 fragments phery_emac0:EMAC_PHY_RXD(0:0)} hps_io_phery_emac0_RXD1 {width 1 properties {} instance_name hps_io internal_name hps_io_phery_emac0_RXD1 direction input role hps_io_phery_emac0_RXD1 fragments phery_emac0:EMAC_PHY_RXD(1:1)} hps_io_phery_emac0_RXD2 {width 1 properties {} instance_name hps_io internal_name hps_io_phery_emac0_RXD2 direction input role hps_io_phery_emac0_RXD2 fragments phery_emac0:EMAC_PHY_RXD(2:2)} hps_io_phery_emac0_RXD3 {width 1 properties {} instance_name hps_io internal_name hps_io_phery_emac0_RXD3 direction input role hps_io_phery_emac0_RXD3 fragments phery_emac0:EMAC_PHY_RXD(3:3)} hps_io_phery_emac0_MDIO {tristate_output {{intermediate 1} {intermediate 0}} width 1 properties {} instance_name hps_io internal_name hps_io_phery_emac0_MDIO direction bidir role hps_io_phery_emac0_MDIO fragments phery_emac0:EMAC_GMII_MDO_I(0:0)} hps_io_phery_emac0_MDC {width 1 properties {} instance_name hps_io internal_name hps_io_phery_emac0_MDC direction output role hps_io_phery_emac0_MDC fragments phery_emac0:EMAC_GMII_MDC(0:0)} hps_io_phery_qspi_IO0 {tristate_output {{intermediate 3} {intermediate 2}} width 1 properties {} instance_name hps_io internal_name hps_io_phery_qspi_IO0 direction bidir role hps_io_phery_qspi_IO0 fragments phery_qspi:QSPI_MI0(0:0)} hps_io_phery_qspi_IO1 {tristate_output {{intermediate 5} {intermediate 4}} width 1 properties {} instance_name hps_io internal_name hps_io_phery_qspi_IO1 direction bidir role hps_io_phery_qspi_IO1 fragments phery_qspi:QSPI_MI1(0:0)} hps_io_phery_qspi_IO2_WPN {tristate_output {{intermediate 7} {intermediate 6}} width 1 properties {} instance_name hps_io internal_name hps_io_phery_qspi_IO2_WPN direction bidir role hps_io_phery_qspi_IO2_WPN fragments phery_qspi:QSPI_MI2(0:0)} hps_io_phery_qspi_IO3_HOLD {tristate_output {{intermediate 9} {intermediate 8}} width 1 properties {} instance_name hps_io internal_name hps_io_phery_qspi_IO3_HOLD direction bidir role hps_io_phery_qspi_IO3_HOLD fragments phery_qspi:QSPI_MI3(0:0)} hps_io_phery_qspi_CLK {width 1 properties {} instance_name hps_io internal_name hps_io_phery_qspi_CLK direction output role hps_io_phery_qspi_CLK fragments phery_qspi:QSPI_SCLK(0:0)} hps_io_phery_qspi_SS0 {width 1 properties {} instance_name hps_io internal_name hps_io_phery_qspi_SS0 direction output role hps_io_phery_qspi_SS0 fragments phery_qspi:QSPI_SS_N(0:0)} hps_io_phery_usb0_DATA0 {tristate_output {{intermediate 11} {intermediate 10}} width 1 properties {} instance_name hps_io internal_name hps_io_phery_usb0_DATA0 direction bidir role hps_io_phery_usb0_DATA0 fragments phery_usb0:USB_ULPI_DATA_I(0:0)} hps_io_phery_usb0_DATA1 {tristate_output {{intermediate 13} {intermediate 12}} width 1 properties {} instance_name hps_io internal_name hps_io_phery_usb0_DATA1 direction bidir role hps_io_phery_usb0_DATA1 fragments phery_usb0:USB_ULPI_DATA_I(1:1)} hps_io_phery_usb0_DATA2 {tristate_output {{intermediate 15} {intermediate 14}} width 1 properties {} instance_name hps_io internal_name hps_io_phery_usb0_DATA2 direction bidir role hps_io_phery_usb0_DATA2 fragments phery_usb0:USB_ULPI_DATA_I(2:2)} hps_io_phery_usb0_DATA3 {tristate_output {{intermediate 17} {intermediate 16}} width 1 properties {} instance_name hps_io internal_name hps_io_phery_usb0_DATA3 direction bidir role hps_io_phery_usb0_DATA3 fragments phery_usb0:USB_ULPI_DATA_I(3:3)} hps_io_phery_usb0_DATA4 {tristate_output {{intermediate 19} {intermediate 18}} width 1 properties {} instance_name hps_io internal_name hps_io_phery_usb0_DATA4 direction bidir role hps_io_phery_usb0_DATA4 fragments phery_usb0:USB_ULPI_DATA_I(4:4)} hps_io_phery_usb0_DATA5 {tristate_output {{intermediate 21} {intermediate 20}} width 1 properties {} instance_name hps_io internal_name hps_io_phery_usb0_DATA5 direction bidir role hps_io_phery_usb0_DATA5 fragments phery_usb0:USB_ULPI_DATA_I(5:5)} hps_io_phery_usb0_DATA6 {tristate_output {{intermediate 23} {intermediate 22}} width 1 properties {} instance_name hps_io internal_name hps_io_phery_usb0_DATA6 direction bidir role hps_io_phery_usb0_DATA6 fragments phery_usb0:USB_ULPI_DATA_I(6:6)} hps_io_phery_usb0_DATA7 {tristate_output {{intermediate 25} {intermediate 24}} width 1 properties {} instance_name hps_io internal_name hps_io_phery_usb0_DATA7 direction bidir role hps_io_phery_usb0_DATA7 fragments phery_usb0:USB_ULPI_DATA_I(7:7)} hps_io_phery_usb0_CLK {width 1 properties {} instance_name hps_io internal_name hps_io_phery_usb0_CLK direction input role hps_io_phery_usb0_CLK fragments phery_usb0:USB_ULPI_CLK(0:0)} hps_io_phery_usb0_STP {width 1 properties {} instance_name hps_io internal_name hps_io_phery_usb0_STP direction output role hps_io_phery_usb0_STP fragments phery_usb0:USB_ULPI_STP(0:0)} hps_io_phery_usb0_DIR {width 1 properties {} instance_name hps_io internal_name hps_io_phery_usb0_DIR direction input role hps_io_phery_usb0_DIR fragments phery_usb0:USB_ULPI_DIR(0:0)} hps_io_phery_usb0_NXT {width 1 properties {} instance_name hps_io internal_name hps_io_phery_usb0_NXT direction input role hps_io_phery_usb0_NXT fragments phery_usb0:USB_ULPI_NXT(0:0)} hps_io_phery_spim1_CLK {width 1 properties {} instance_name hps_io internal_name hps_io_phery_spim1_CLK direction output role hps_io_phery_spim1_CLK fragments phery_spim1:SPI_MASTER_SCLK(0:0)} hps_io_phery_spim1_MOSI {tristate_output {{intermediate 27} {intermediate 26}} width 1 properties {} instance_name hps_io internal_name hps_io_phery_spim1_MOSI direction output role hps_io_phery_spim1_MOSI fragments {}} hps_io_phery_spim1_MISO {width 1 properties {} instance_name hps_io internal_name hps_io_phery_spim1_MISO direction input role hps_io_phery_spim1_MISO fragments phery_spim1:SPI_MASTER_RXD(0:0)} hps_io_phery_spim1_SS0_N {width 1 properties {} instance_name hps_io internal_name hps_io_phery_spim1_SS0_N direction output role hps_io_phery_spim1_SS0_N fragments phery_spim1:SPI_MASTER_SS_0_N(0:0)} hps_io_phery_spim1_SS1_N {width 1 properties {} instance_name hps_io internal_name hps_io_phery_spim1_SS1_N direction output role hps_io_phery_spim1_SS1_N fragments phery_spim1:SPI_MASTER_SS_1_N(0:0)} hps_io_phery_trace_CLK {width 1 properties {} instance_name hps_io internal_name hps_io_phery_trace_CLK direction output role hps_io_phery_trace_CLK fragments phery_trace:TPIU_TRACE_CLK(0:0)} hps_io_phery_trace_D0 {width 1 properties {} instance_name hps_io internal_name hps_io_phery_trace_D0 direction output role hps_io_phery_trace_D0 fragments phery_trace:TPIU_TRACE_DATA(0:0)} hps_io_phery_trace_D1 {width 1 properties {} instance_name hps_io internal_name hps_io_phery_trace_D1 direction output role hps_io_phery_trace_D1 fragments phery_trace:TPIU_TRACE_DATA(1:1)} hps_io_phery_trace_D2 {width 1 properties {} instance_name hps_io internal_name hps_io_phery_trace_D2 direction output role hps_io_phery_trace_D2 fragments phery_trace:TPIU_TRACE_DATA(2:2)} hps_io_phery_trace_D3 {width 1 properties {} instance_name hps_io internal_name hps_io_phery_trace_D3 direction output role hps_io_phery_trace_D3 fragments phery_trace:TPIU_TRACE_DATA(3:3)} hps_io_phery_uart1_RX {width 1 properties {} instance_name hps_io internal_name hps_io_phery_uart1_RX direction input role hps_io_phery_uart1_RX fragments phery_uart1:UART_RXD(0:0)} hps_io_phery_uart1_TX {width 1 properties {} instance_name hps_io internal_name hps_io_phery_uart1_TX direction output role hps_io_phery_uart1_TX fragments phery_uart1:UART_TXD(0:0)} hps_io_phery_i2c1_SDA {tristate_output {{intermediate 28} {}} width 1 properties {} instance_name hps_io internal_name hps_io_phery_i2c1_SDA direction bidir role hps_io_phery_i2c1_SDA fragments phery_i2c1:I2C_DATA(0:0)} hps_io_phery_i2c1_SCL {tristate_output {{intermediate 29} {}} width 1 properties {} instance_name hps_io internal_name hps_io_phery_i2c1_SCL direction bidir role hps_io_phery_i2c1_SCL fragments phery_i2c1:I2C_CLK(0:0)} hps_io_gpio_gpio1_io5 {tristate_output {{intermediate 31} {intermediate 30}} width 1 properties {} instance_name hps_io internal_name hps_io_gpio_gpio1_io5 direction bidir role hps_io_gpio_gpio1_io5 fragments gpio:GPIO1_PORTA_I(5:5)} hps_io_gpio_gpio1_io14 {tristate_output {{intermediate 33} {intermediate 32}} width 1 properties {} instance_name hps_io internal_name hps_io_gpio_gpio1_io14 direction bidir role hps_io_gpio_gpio1_io14 fragments gpio:GPIO1_PORTA_I(14:14)} hps_io_gpio_gpio1_io16 {tristate_output {{intermediate 35} {intermediate 34}} width 1 properties {} instance_name hps_io internal_name hps_io_gpio_gpio1_io16 direction bidir role hps_io_gpio_gpio1_io16 fragments gpio:GPIO1_PORTA_I(16:16)} hps_io_gpio_gpio1_io17 {tristate_output {{intermediate 37} {intermediate 36}} width 1 properties {} instance_name hps_io internal_name hps_io_gpio_gpio1_io17 direction bidir role hps_io_gpio_gpio1_io17 fragments gpio:GPIO1_PORTA_I(17:17)}}}} properties {GENERATE_ISW 1} interface_sim_style {} raw_assigns {} intermediate_wire_count 38 raw_assign_sim_style {} wires_to_fragments {{intermediate 23} {output phery_usb0:USB_ULPI_DATA_OE(6:6)} {intermediate 24} {output phery_usb0:USB_ULPI_DATA_O(7:7)} {intermediate 25} {output phery_usb0:USB_ULPI_DATA_OE(7:7)} {intermediate 26} {output phery_spim1:SPI_MASTER_TXD(0:0)} {intermediate 0} {output phery_emac0:EMAC_GMII_MDO_O(0:0)} {intermediate 27} {output phery_spim1:SPI_MASTER_SSI_OE_N(0:0)} {intermediate 1} {output phery_emac0:EMAC_GMII_MDO_OE(0:0)} {intermediate 10} {output phery_usb0:USB_ULPI_DATA_O(0:0)} {intermediate 28} {output phery_i2c1:I2C_DATA_OE(0:0)} {intermediate 2} {output phery_qspi:QSPI_MO0(0:0)} {intermediate 11} {output phery_usb0:USB_ULPI_DATA_OE(0:0)} {intermediate 30} {output gpio:GPIO1_PORTA_O(5:5)} {intermediate 29} {output phery_i2c1:I2C_CLK_OE(0:0)} {intermediate 12} {output phery_usb0:USB_ULPI_DATA_O(1:1)} {intermediate 3} {output phery_qspi:QSPI_MO_EN_N(0:0)} {intermediate 31} {output gpio:GPIO1_PORTA_OE(5:5)} {intermediate 13} {output phery_usb0:USB_ULPI_DATA_OE(1:1)} {intermediate 4} {output phery_qspi:QSPI_MO1(0:0)} {intermediate 32} {output gpio:GPIO1_PORTA_O(14:14)} {intermediate 14} {output phery_usb0:USB_ULPI_DATA_O(2:2)} {intermediate 5} {output phery_qspi:QSPI_MO_EN_N(1:1)} {intermediate 33} {output gpio:GPIO1_PORTA_OE(14:14)} {intermediate 15} {output phery_usb0:USB_ULPI_DATA_OE(2:2)} {intermediate 6} {output phery_qspi:QSPI_MO2(0:0)} {intermediate 34} {output gpio:GPIO1_PORTA_O(16:16)} {intermediate 16} {output phery_usb0:USB_ULPI_DATA_O(3:3)} {intermediate 7} {output phery_qspi:QSPI_MO_EN_N(2:2)} {intermediate 35} {output gpio:GPIO1_PORTA_OE(16:16)} {intermediate 17} {output phery_usb0:USB_ULPI_DATA_OE(3:3)} {intermediate 8} {output phery_qspi:QSPI_MO3(0:0)} {intermediate 36} {output gpio:GPIO1_PORTA_O(17:17)} {intermediate 18} {output phery_usb0:USB_ULPI_DATA_O(4:4)} {intermediate 9} {output phery_qspi:QSPI_MO_EN_N(3:3)} {intermediate 37} {output gpio:GPIO1_PORTA_OE(17:17)} {intermediate 20} {output phery_usb0:USB_ULPI_DATA_O(5:5)} {intermediate 19} {output phery_usb0:USB_ULPI_DATA_OE(4:4)} {intermediate 21} {output phery_usb0:USB_ULPI_DATA_OE(5:5)} {intermediate 22} {output phery_usb0:USB_ULPI_DATA_O(6:6)}} wire_sim_style {} hps_parameter_map H2F_DEBUG_APB_CLOCK_FREQ 100 quartus_ini_hps_ip_enable_jtag false MAINPLLGRP_NOC_CNT 11 SPIS1_Mode N/A MAINPLLGRP_SDMMC_CNT 900 test_iface_definition {DFT_IN_ADVANCE 1 input DFT_IN_ATPG_CLK_SEL_N 1 input DFT_IN_ATPG_MODE_N 1 input DFT_IN_BIST_CPU_SI 1 input DFT_IN_BIST_L2_SI 1 input DFT_IN_BIST_PERI_SI 3 input DFT_IN_BIST_RST_N 1 input DFT_IN_BIST_SE_N 1 input DFT_IN_BISTCLK 1 input DFT_IN_BISTEN_N 1 input DFT_IN_BWADJ 12 input DFT_IN_CLKF 13 input DFT_IN_CLKOD 11 input DFT_IN_CLKOD_CTL 1 input DFT_IN_CLKOD_SCANCLK 1 input DFT_IN_CLKOD_SCANIN 1 input DFT_IN_CLKR 6 input DFT_IN_COMPRESS_ENABLE_N 1 input DFT_IN_ECCBYP_N 1 input DFT_IN_ENSAT 1 input DFT_IN_FASTEN 1 input DFT_IN_FREECLK_EN_N 1 input DFT_IN_IO_CONTROL 20 input DFT_IN_IO_INTERFACE_TEST_MODE_N 1 input DFT_IN_IO_TEST_MODE_N 1 input DFT_IN_JTAG_MODE 1 input DFT_IN_JTAG_UPDATE_DR 1 input DFT_IN_JTGHIGHZ 1 input DFT_IN_L4MPCLK_DIV_CTL_N 1 input DFT_IN_MAINPLL_BG_PWRDN 1 input DFT_IN_MAINPLL_BG_RESET 1 input DFT_IN_MAINPLL_REG_PWRDN 1 input DFT_IN_MAINPLL_REG_RESET 1 input DFT_IN_MAINPLL_REG_TEST_SEL 1 input DFT_IN_MEM_CPU_SI 1 input DFT_IN_MEM_L2_SI 1 input DFT_IN_MEM_PERI_SI 3 input DFT_IN_MEM_SE_N 1 input DFT_IN_MPFE_ATPG_MODE_N 1 input DFT_IN_MPFE_CLK_SEL_N 1 input DFT_IN_MPFE_IO_INTERFACE_TEST_MODE_N 1 input DFT_IN_MPFE_OCC_BYPASS_N 1 input DFT_IN_MPFE_OCC_ENABLE_N 1 input DFT_IN_MPFE_OCC_SI 1 input DFT_IN_MPFE_PIPELINE_SCAN_EN_N 1 input DFT_IN_MPFE_SCANEN_N 1 input DFT_IN_MPFE_SCANIN 14 input DFT_IN_MPFE_TEST_CLK_0 1 input DFT_IN_MPFE_TEST_CLK_1 1 input DFT_IN_MPFE_TEST_CLK_2 1 input DFT_IN_MPFE_TEST_CLOCK_EN_N 1 input DFT_IN_MPFE_TEST_MODE_N 1 input DFT_IN_MTESTEN_N 1 input DFT_IN_NOC_LEFT_SCANIN 15 input DFT_IN_NOC_RIGHT_SCANIN 10 input DFT_IN_OCC_ENABLE_N 1 input DFT_IN_OUTRESET 1 input DFT_IN_OUTRESETALL 1 input DFT_IN_PERIPHPLL_BG_PWRDN 1 input DFT_IN_PERIPHPLL_BG_RESET 1 input DFT_IN_PERIPHPLL_REG_PWRDN 1 input DFT_IN_PERIPHPLL_REG_RESET 1 input DFT_IN_PERIPHPLL_REG_TEST_SEL 1 input DFT_IN_PINMUX_SCANEN 1 input DFT_IN_PINMUX_SCANIN 1 input DFT_IN_PIPELINE_SCAN_EN_N 1 input DFT_IN_PLL_CLK_TESTBUS_SEL 4 input DFT_IN_PLL_DEBUG_TESTBUS_SEL 4 input DFT_IN_PLL_REG_EXT_SEL 1 input DFT_IN_PLL_REG_TEST_DRV 1 input DFT_IN_PLL_REG_TEST_OUT 1 input DFT_IN_PLL_REG_TEST_REP 1 input DFT_IN_PLLBYPASS 1 input DFT_IN_PLLBYPASS_SEL_N 1 input DFT_IN_PLLTEST_INPUT_EN_N 1 input DFT_IN_PRBS_TEST_ENABLE_N 1 input DFT_IN_PWRDN 1 input DFT_IN_REG_TEST_INT_EN_N 1 input DFT_IN_RESET 1 input DFT_IN_SCANEN_N 1 input DFT_IN_STEP 1 input DFT_IN_TCK 1 input DFT_IN_TDI 1 input DFT_IN_TEST 1 input DFT_IN_TEST_CLOCK 1 input DFT_IN_TEST_CLOCK_EN_N 60 input DFT_IN_TEST_INIT_N 1 input DFT_IN_TEST_SI 50 input DFT_IN_TESTMODE_N 1 input DFX_IN_RINGO_DATAIN 1 input DFX_IN_RINGO_ENABLE_N 1 input DFX_IN_RINGO_SCAN_EN_N 1 input DFX_IN_T2_CLK 1 input DFX_IN_T2_DATAIN 1 input DFX_IN_T2_SCAN_EN_N 1 input DFT_OUT_BIST_CPU_SO 1 output DFT_OUT_BIST_L2_SO 1 output DFT_OUT_BIST_PERI_SO 3 output DFT_OUT_CLKOD_SCANOUT 1 output DFT_OUT_MAINPLL_CLKOUT_0_7 1 output DFT_OUT_MAINPLL_CLKOUT_8_15 1 output DFT_OUT_MAINPLL_DEBUGOUT 1 output DFT_OUT_MAINPLL_REG_TEST_INT 1 output DFT_OUT_MAINPLL_REG_TEST_SIG 1 output DFT_OUT_MEM_CPU_SO 1 output DFT_OUT_MEM_L2_SO 1 output DFT_OUT_MEM_PERI_SO 3 output DFT_OUT_MPFE_OCC_SO 1 output DFT_OUT_MPFE_SCANOUT 14 output DFT_OUT_NOC_LEFT_SCANOUT 15 output DFT_OUT_NOC_RIGHT_SCANOUT 10 output DFT_OUT_PERIPHPLL_CLKOUT_0_7 1 output DFT_OUT_PERIPHPLL_CLKOUT_8_15 1 output DFT_OUT_PERIPHPLL_DEBUGOUT 1 output DFT_OUT_PERIPHPLL_REG_TEST_INT 1 output DFT_OUT_PERIPHPLL_REG_TEST_SIG 1 output DFT_OUT_PINMUX_SCANOUT 1 output DFT_OUT_SECMGR_POR_RST_N 1 output DFT_OUT_TDO 1 output DFT_OUT_TEST_SO 50 output DFT_OUT_TESTMODE_STATUS 1 output DFX_OUT_DCLK 1 output DFX_OUT_FPGA_DATA 18 output DFX_OUT_FPGA_L4_SYS_FREE_CLK 1 output DFX_OUT_FPGA_S2F_NTRST 1 output DFX_OUT_PR_REQUEST 1 output DFX_OUT_RINGO_DATAOUT 1 output DFX_OUT_S2F_DATA 32 output DFX_OUT_T2_DATAOUT 4 output} H2F_AXI_CLOCK_FREQ 100000000 I2CEMAC0_PinMuxing Unused QSPI_PinMuxing IO MAINPLLGRP_MPU_CNT 1 quartus_ini_hps_ip_enable_a10_advanced_options false CLK_SDMMC_SOURCE 1 JAVA_WARNING_MSG {} S2FINTERRUPT_NAND_Enable false JAVA_ERROR_MSG {} I2CEMAC2_Mode N/A CLK_EMAC_PTP_SOURCE 1 DB_iface_ports {emac0_tx_clk_in {@orderednames emac0_clk_tx_i emac0_clk_tx_i {direction Input atom_signal_name clk_tx_i role clk}} emac0_gtx_clk {emac0_phy_txclk_o {direction Output atom_signal_name s2f_clk role clk} @orderednames emac0_phy_txclk_o} spim0 {spim0_ss3_n_o {direction Output atom_signal_name ss3_n_o role ss3_n_o} spim0_miso_i {direction Input atom_signal_name miso_i role miso_i} @orderednames {spim0_mosi_o spim0_miso_i spim0_ss_in_n spim0_mosi_oe spim0_ss0_n_o spim0_ss1_n_o spim0_ss2_n_o spim0_ss3_n_o} spim0_ss_in_n {direction Input atom_signal_name ss_in_n role ss_in_n} spim0_ss0_n_o {direction Output atom_signal_name ss0_n_o role ss0_n_o} spim0_ss1_n_o {direction Output atom_signal_name ss1_n_o role ss1_n_o} spim0_mosi_o {direction Output atom_signal_name mosi_o role mosi_o} spim0_mosi_oe {direction Output atom_signal_name mosi_oe role mosi_oe} spim0_ss2_n_o {direction Output atom_signal_name ss2_n_o role ss2_n_o}} emac1_gtx_clk {@orderednames emac1_phy_txclk_o emac1_phy_txclk_o {direction Output atom_signal_name s2f_clk role clk}} spim1 {spim1_mosi_oe {direction Output atom_signal_name mosi_oe role mosi_oe} spim1_ss2_n_o {direction Output atom_signal_name ss2_n_o role ss2_n_o} spim1_ss3_n_o {direction Output atom_signal_name ss3_n_o role ss3_n_o} spim1_miso_i {direction Input atom_signal_name miso_i role miso_i} @orderednames {spim1_mosi_o spim1_miso_i spim1_ss_in_n spim1_mosi_oe spim1_ss0_n_o spim1_ss1_n_o spim1_ss2_n_o spim1_ss3_n_o} spim1_ss_in_n {direction Input atom_signal_name ss_in_n role ss_in_n} spim1_ss0_n_o {direction Output atom_signal_name ss0_n_o role ss0_n_o} spim1_ss1_n_o {direction Output atom_signal_name ss1_n_o role ss1_n_o} spim1_mosi_o {direction Output atom_signal_name mosi_o role mosi_o}} emac2_gtx_clk {@orderednames emac2_phy_txclk_o emac2_phy_txclk_o {direction Output atom_signal_name s2f_clk role clk}} sdmmc_clk_in {@orderednames sdmmc_clk_in sdmmc_clk_in {direction Input atom_signal_name clk_in role clk}} i2cemac1_scl_in {i2c_emac1_scl_i {direction Input atom_signal_name scl_i role clk} @orderednames i2c_emac1_scl_i} spim0_sclk_out {spim0_sclk_out {direction Output atom_signal_name sclk_out role clk} @orderednames spim0_sclk_out} qspi {qspi_ss_o {direction Output atom_signal_name ss_o role ss_o} qspi_io0_i {direction Input atom_signal_name io0_i role io0_i} qspi_io2_wpn_o {direction Output atom_signal_name io2_wpn_o role io2_wpn_o} qspi_io1_i {direction Input atom_signal_name io1_i role io1_i} @orderednames {qspi_io0_i qspi_io1_i qspi_io2_i qspi_io3_i qspi_io0_o qspi_io1_o qspi_io2_wpn_o qspi_io3_hold_o qspi_mo_oe qspi_ss_o} qspi_io2_i {direction Input atom_signal_name io2_i role io2_i} qspi_io0_o {direction Output atom_signal_name io0_o role io0_o} qspi_io3_hold_o {direction Output atom_signal_name io3_hold_o role io3_hold_o} qspi_io1_o {direction Output atom_signal_name io1_o role io1_o} qspi_io3_i {direction Input atom_signal_name io3_i role io3_i} qspi_mo_oe {direction Output atom_signal_name mo_oe role mo_oe}} i2cemac1_clk {i2c_emac1_scl_oe {direction Output atom_signal_name scl_oe role clk} @orderednames i2c_emac1_scl_oe} emac0 {emac0_ptp_aux_ts_trig_i {direction Input atom_signal_name ptp_aux_ts_trig_i role ptp_aux_ts_trig_i} emac0_ptp_pps_o {direction Output atom_signal_name ptp_pps_o role ptp_pps_o} @orderednames {emac0_phy_txd_o emac0_phy_mac_speed_o emac0_phy_txen_o emac0_phy_txer_o emac0_phy_rxdv_i emac0_phy_rxer_i emac0_phy_rxd_i emac0_phy_col_i emac0_phy_crs_i emac0_gmii_mdo_o emac0_gmii_mdo_o_e emac0_gmii_mdi_i emac0_ptp_pps_o emac0_ptp_aux_ts_trig_i emac0_ptp_tstmp_data emac0_ptp_tstmp_en} emac0_phy_rxdv_i {direction Input atom_signal_name phy_rxdv_i role phy_rxdv_i} emac0_phy_rxd_i {direction Input atom_signal_name phy_rxd_i role phy_rxd_i} emac0_phy_mac_speed_o {direction Output atom_signal_name phy_mac_speed_o role phy_mac_speed_o} emac0_gmii_mdo_o_e {direction Output atom_signal_name gmii_mdo_o_e role gmii_mdo_o_e} emac0_phy_rxer_i {direction Input atom_signal_name phy_rxer_i role phy_rxer_i} emac0_gmii_mdo_o {direction Output atom_signal_name gmii_mdo_o role gmii_mdo_o} emac0_ptp_tstmp_data {direction Output atom_signal_name ptp_tstmp_data role ptp_tstmp_data} emac0_ptp_tstmp_en {direction Output atom_signal_name ptp_tstmp_en role ptp_tstmp_en} emac0_phy_txen_o {direction Output atom_signal_name phy_txen_o role phy_txen_o} emac0_phy_txd_o {direction Output atom_signal_name phy_txd_o role phy_txd_o} emac0_phy_col_i {direction Input atom_signal_name phy_col_i role phy_col_i} emac0_gmii_mdi_i {direction Input atom_signal_name gmii_mdi_i role gmii_mdi_i} emac0_phy_crs_i {direction Input atom_signal_name phy_crs_i role phy_crs_i} emac0_phy_txer_o {direction Output atom_signal_name phy_txer_o role phy_txer_o}} emac1 {emac1_gmii_mdo_o {direction Output atom_signal_name gmii_mdo_o role gmii_mdo_o} @orderednames {emac1_phy_mac_speed_o emac1_phy_txd_o emac1_phy_txen_o emac1_phy_txer_o emac1_phy_rxdv_i emac1_phy_rxer_i emac1_phy_rxd_i emac1_phy_col_i emac1_phy_crs_i emac1_gmii_mdo_o emac1_gmii_mdo_o_e emac1_gmii_mdi_i emac1_ptp_pps_o emac1_ptp_aux_ts_trig_i emac1_ptp_tstmp_data emac1_ptp_tstmp_en} emac1_ptp_tstmp_data {direction Output atom_signal_name ptp_tstmp_data role ptp_tstmp_data} emac1_ptp_aux_ts_trig_i {direction Input atom_signal_name ptp_aux_ts_trig_i role ptp_aux_ts_trig_i} emac1_ptp_pps_o {direction Output atom_signal_name ptp_pps_o role ptp_pps_o} emac1_ptp_tstmp_en {direction Output atom_signal_name ptp_tstmp_en role ptp_tstmp_en} emac1_phy_txen_o {direction Output atom_signal_name phy_txen_o role phy_txen_o} emac1_phy_rxd_i {direction Input atom_signal_name phy_rxd_i role phy_rxd_i} emac1_gmii_mdi_i {direction Input atom_signal_name gmii_mdi_i role gmii_mdi_i} emac1_phy_mac_speed_o {direction Output atom_signal_name phy_mac_speed_o role phy_mac_speed_o} emac1_phy_txer_o {direction Output atom_signal_name phy_txer_o role phy_txer_o} emac1_phy_rxdv_i {direction Input atom_signal_name phy_rxdv_i role phy_rxdv_i} emac1_phy_txd_o {direction Output atom_signal_name phy_txd_o role phy_txd_o} emac1_phy_col_i {direction Input atom_signal_name phy_col_i role phy_col_i} emac1_gmii_mdo_o_e {direction Output atom_signal_name gmii_mdo_o_e role gmii_mdo_o_e} emac1_phy_crs_i {direction Input atom_signal_name phy_crs_i role phy_crs_i} emac1_phy_rxer_i {direction Input atom_signal_name phy_rxer_i role phy_rxer_i}} emac2 {emac2_phy_txer_o {direction Output atom_signal_name phy_txer_o role phy_txer_o} @orderednames {emac2_phy_mac_speed_o emac2_phy_txd_o emac2_phy_txen_o emac2_phy_txer_o emac2_phy_rxdv_i emac2_phy_rxer_i emac2_phy_rxd_i emac2_phy_col_i emac2_phy_crs_i emac2_gmii_mdo_o emac2_gmii_mdo_o_e emac2_gmii_mdi_i emac2_ptp_pps_o emac2_ptp_aux_ts_trig_i emac2_ptp_tstmp_data emac2_ptp_tstmp_en} emac2_ptp_aux_ts_trig_i {direction Input atom_signal_name ptp_aux_ts_trig_i role ptp_aux_ts_trig_i} emac2_ptp_pps_o {direction Output atom_signal_name ptp_pps_o role ptp_pps_o} emac2_phy_rxdv_i {direction Input atom_signal_name phy_rxdv_i role phy_rxdv_i} emac2_phy_rxd_i {direction Input atom_signal_name phy_rxd_i role phy_rxd_i} emac2_phy_mac_speed_o {direction Output atom_signal_name phy_mac_speed_o role phy_mac_speed_o} emac2_gmii_mdo_o_e {direction Output atom_signal_name gmii_mdo_o_e role gmii_mdo_o_e} emac2_phy_rxer_i {direction Input atom_signal_name phy_rxer_i role phy_rxer_i} emac2_gmii_mdo_o {direction Output atom_signal_name gmii_mdo_o role gmii_mdo_o} emac2_ptp_tstmp_data {direction Output atom_signal_name ptp_tstmp_data role ptp_tstmp_data} emac2_ptp_tstmp_en {direction Output atom_signal_name ptp_tstmp_en role ptp_tstmp_en} emac2_phy_txen_o {direction Output atom_signal_name phy_txen_o role phy_txen_o} emac2_phy_col_i {direction Input atom_signal_name phy_col_i role phy_col_i} emac2_phy_txd_o {direction Output atom_signal_name phy_txd_o role phy_txd_o} emac2_gmii_mdi_i {direction Input atom_signal_name gmii_mdi_i role gmii_mdi_i} emac2_phy_crs_i {direction Input atom_signal_name phy_crs_i role phy_crs_i}} spis0_sclk_in {spis0_sclk_in {direction Input atom_signal_name clk role clk} @orderednames spis0_sclk_in} spis1_sclk_in {@orderednames spis1_sclk_in spis1_sclk_in {direction Input atom_signal_name clk role clk}} trace_s2f_clk {@orderednames trace_s2f_clk trace_s2f_clk {direction Output atom_signal_name s2f_clk role clk}} i2cemac0_scl_in {i2c_emac0_scl_i {direction Input atom_signal_name scl_i role clk} @orderednames i2c_emac0_scl_i} emac0_tx_reset {emac0_rst_clk_tx_n_o {direction Output atom_signal_name rst_clk_tx_n_o role reset_n} @orderednames emac0_rst_clk_tx_n_o} sdmmc {@orderednames {sdmmc_vs_o sdmmc_pwr_ena_o sdmmc_wp_i sdmmc_cdn_i sdmmc_card_intn_i sdmmc_cmd_i sdmmc_cmd_o sdmmc_cmd_oe sdmmc_data_i sdmmc_data_o sdmmc_data_oe} sdmmc_cmd_oe {direction Output atom_signal_name cmd_oe role cmd_oe} sdmmc_pwr_ena_o {direction Output atom_signal_name pwr_ena_o role pwr_ena_o} sdmmc_card_intn_i {direction Input atom_signal_name card_intn_i role card_intn_i} sdmmc_cmd_o {direction Output atom_signal_name cmd_o role cmd_o} sdmmc_data_i {direction Input atom_signal_name data_i role data_i} sdmmc_cdn_i {direction Input atom_signal_name cdn_i role cdn_i} sdmmc_data_oe {direction Output atom_signal_name data_oe role data_oe} sdmmc_vs_o {direction Output atom_signal_name vs_o role vs_o} sdmmc_wp_i {direction Input atom_signal_name wp_i role wp_i} sdmmc_data_o {direction Output atom_signal_name data_o role data_o} sdmmc_cmd_i {direction Input atom_signal_name cmd_i role cmd_i}} spim1_sclk_out {spim1_sclk_out {direction Output atom_signal_name sclk_out role clk} @orderednames spim1_sclk_out} emac1_rx_clk_in {emac1_clk_rx_i {direction Input atom_signal_name clk_rx_i role clk} @orderednames emac1_clk_rx_i} i2c0_clk {@orderednames i2c0_scl_oe i2c0_scl_oe {direction Output atom_signal_name scl_oe role clk}} emac1_tx_clk_in {@orderednames emac1_clk_tx_i emac1_clk_tx_i {direction Input atom_signal_name clk_tx_i role clk}} i2cemac0 {i2c_emac0_sda_oe {direction Output atom_signal_name sda_oe role sda_oe} @orderednames {i2c_emac0_sda_i i2c_emac0_sda_oe} i2c_emac0_sda_i {direction Input atom_signal_name sda_i role sda_i}} emac1_tx_reset {@orderednames emac1_rst_clk_tx_n_o emac1_rst_clk_tx_n_o {direction Output atom_signal_name rst_clk_tx_n_o role reset_n}} i2cemac1 {@orderednames {i2c_emac1_sda_i i2c_emac1_sda_oe} i2c_emac1_sda_oe {direction Output atom_signal_name sda_oe role sda_oe} i2c_emac1_sda_i {direction Input atom_signal_name sda_i role sda_i}} i2cemac2 {i2c_emac2_sda_i {direction Input atom_signal_name sda_i role sda_i} @orderednames {i2c_emac2_sda_i i2c_emac2_sda_oe} i2c_emac2_sda_oe {direction Output atom_signal_name sda_oe role sda_oe}} emac0_rx_reset {@orderednames emac0_rst_clk_rx_n_o emac0_rst_clk_rx_n_o {direction Output atom_signal_name rst_clk_rx_n_o role reset_n}} emac2_tx_reset {@orderednames emac2_rst_clk_tx_n_o emac2_rst_clk_tx_n_o {direction Output atom_signal_name rst_clk_tx_n_o role reset_n}} i2c1_scl_in {i2c1_scl_i {direction Input atom_signal_name scl_i role clk} @orderednames i2c1_scl_i} emac2_rx_clk_in {@orderednames emac2_clk_rx_i emac2_clk_rx_i {direction Input atom_signal_name clk_rx_i role clk}} sdmmc_cclk {@orderednames sdmmc_cclk_out sdmmc_cclk_out {direction Output atom_signal_name cclk_o role clk}} emac2_md_clk {@orderednames emac2_gmii_mdc_o emac2_gmii_mdc_o {direction Output atom_signal_name gmii_mdc_o role clk}} emac1_rx_reset {emac1_rst_clk_rx_n_o {direction Output atom_signal_name rst_clk_rx_n_o role reset_n} @orderednames emac1_rst_clk_rx_n_o} emac2_tx_clk_in {emac2_clk_tx_i {direction Input atom_signal_name clk_tx_i role clk} @orderednames emac2_clk_tx_i} uart0 {uart0_out1_n {direction Output atom_signal_name out1_n role out1_n} uart0_dsr_n {direction Input atom_signal_name dsr_n role dsr_n} @orderednames {uart0_cts_n uart0_dsr_n uart0_dcd_n uart0_ri_n uart0_rx uart0_dtr_n uart0_rts_n uart0_out1_n uart0_out2_n uart0_tx} uart0_rx {direction Input atom_signal_name rx role rx} uart0_rts_n {direction Output atom_signal_name rts_n role rts_n} uart0_dtr_n {direction Output atom_signal_name dtr_n role dtr_n} uart0_cts_n {direction Input atom_signal_name cts_n role cts_n} uart0_out2_n {direction Output atom_signal_name out2_n role out2_n} uart0_tx {direction Output atom_signal_name tx role tx} uart0_ri_n {direction Input atom_signal_name ri_n role ri_n} uart0_dcd_n {direction Input atom_signal_name dcd_n role dcd_n}} i2cemac0_clk {@orderednames i2c_emac0_scl_oe i2c_emac0_scl_oe {direction Output atom_signal_name scl_oe role clk}} uart1 {uart1_tx {direction Output atom_signal_name tx role tx} uart1_ri_n {direction Input atom_signal_name ri_n role ri_n} uart1_dcd_n {direction Input atom_signal_name dcd_n role dcd_n} @orderednames {uart1_cts_n uart1_dsr_n uart1_dcd_n uart1_ri_n uart1_rx uart1_dtr_n uart1_rts_n uart1_out1_n uart1_out2_n uart1_tx} uart1_out1_n {direction Output atom_signal_name out1_n role out1_n} uart1_dsr_n {direction Input atom_signal_name dsr_n role dsr_n} uart1_rx {direction Input atom_signal_name rx role rx} uart1_rts_n {direction Output atom_signal_name rts_n role rts_n} uart1_dtr_n {direction Output atom_signal_name dtr_n role dtr_n} uart1_cts_n {direction Input atom_signal_name cts_n role cts_n} uart1_out2_n {direction Output atom_signal_name out2_n role out2_n}} i2c0_scl_in {@orderednames i2c0_scl_i i2c0_scl_i {direction Input atom_signal_name scl_i role clk}} i2cemac2_clk {i2c_emac2_scl_oe {direction Output atom_signal_name scl_oe role clk} @orderednames i2c_emac2_scl_oe} trace {trace_data {direction Output atom_signal_name data role data} @orderednames {trace_clk_ctl trace_clkin trace_data} trace_clk_ctl {direction Input atom_signal_name clk_ctl role clk_ctl} trace_clkin {direction Input atom_signal_name clkin role clkin}} emac1_md_clk {emac1_gmii_mdc_o {direction Output atom_signal_name gmii_mdc_o role clk} @orderednames emac1_gmii_mdc_o} cm {@orderednames {}} qspi_sclk_out {qspi_sclk_out {direction Output atom_signal_name sclk_out role clk} @orderednames qspi_sclk_out} qspi_s2f_clk {qspi_s2f_clk {direction Output atom_signal_name s2f_clk role clk} @orderednames qspi_s2f_clk} emac2_rx_reset {emac2_rst_clk_rx_n_o {direction Output atom_signal_name rst_clk_rx_n_o role reset_n} @orderednames emac2_rst_clk_rx_n_o} emac0_md_clk {emac0_gmii_mdc_o {direction Output atom_signal_name gmii_mdc_o role clk} @orderednames emac0_gmii_mdc_o} i2c1_clk {@orderednames i2c1_scl_oe i2c1_scl_oe {direction Output atom_signal_name scl_oe role clk}} nand {nand_ale_o {direction Output atom_signal_name ale_o role ale_o} nand_adq_o {direction Output atom_signal_name adq_o role adq_o} nand_wp_o {direction Output atom_signal_name wp_n_o role wp_n_o} nand_rdy_busy_i {direction Input atom_signal_name rdy_busy_i role rdy_busy_i} nand_adq_oe {direction Output atom_signal_name adq_oe role adq_oe} @orderednames {nand_adq_i nand_adq_oe nand_adq_o nand_ale_o nand_ce_o nand_cle_o nand_re_o nand_rdy_busy_i nand_we_o nand_wp_o} nand_re_o {direction Output atom_signal_name re_n_o role re_n_o} nand_cle_o {direction Output atom_signal_name cle_o role cle_o} nand_adq_i {direction Input atom_signal_name adq_i role adq_i} nand_ce_o {direction Output atom_signal_name ce_n_o role ce_n_o} nand_we_o {direction Output atom_signal_name we_n_o role we_n_o}} usb0 {usb0_ulpi_nxt {direction Input atom_signal_name ulpi_nxt role ulpi_nxt} usb0_ulpi_data_i {direction Input atom_signal_name ulpi_data_i role ulpi_data_i} usb0_ulpi_stp {direction Output atom_signal_name ulpi_stp role ulpi_stp} @orderednames {usb0_ulpi_dir usb0_ulpi_nxt usb0_ulpi_data_i usb0_ulpi_stp usb0_ulpi_data_o usb0_ulpi_data_oe} usb0_ulpi_dir {direction Input atom_signal_name ulpi_dir role ulpi_dir} usb0_ulpi_data_o {direction Output atom_signal_name ulpi_data_o role ulpi_data_o} usb0_ulpi_data_oe {direction Output atom_signal_name ulpi_data_oe role ulpi_data_oe}} usb1_clk_in {usb1_ulpi_clk {direction Input atom_signal_name ulpi_clk role clk} @orderednames usb1_ulpi_clk} usb1 {usb1_ulpi_data_oe {direction Output atom_signal_name ulpi_data_oe role ulpi_data_oe} usb1_ulpi_nxt {direction Input atom_signal_name ulpi_nxt role ulpi_nxt} @orderednames {usb1_ulpi_dir usb1_ulpi_nxt usb1_ulpi_data_i usb1_ulpi_stp usb1_ulpi_data_o usb1_ulpi_data_oe} usb1_ulpi_data_i {direction Input atom_signal_name ulpi_data_i role ulpi_data_i} usb1_ulpi_stp {direction Output atom_signal_name ulpi_stp role ulpi_stp} usb1_ulpi_dir {direction Input atom_signal_name ulpi_dir role ulpi_dir} usb1_ulpi_data_o {direction Output atom_signal_name ulpi_data_o role ulpi_data_o}} sdmmc_reset {sdmmc_rstn_o {direction Output atom_signal_name rstn_o role reset} @orderednames sdmmc_rstn_o} spis0 {spis0_miso_o {direction Output atom_signal_name miso_o role miso_o} spis0_miso_oe {direction Output atom_signal_name miso_oe role miso_oe} @orderednames {spis0_mosi_i spis0_ss_in_n spis0_miso_o spis0_miso_oe} spis0_mosi_i {direction Input atom_signal_name mosi_i role mosi_i} spis0_ss_in_n {direction Input atom_signal_name ss_in_n role ss_in_n}} spis1 {spis1_ss_in_n {direction Input atom_signal_name ss_in_n role ss_in_n} @orderednames {spis1_mosi_i spis1_ss_in_n spis1_miso_o spis1_miso_oe} spis1_miso_o {direction Output atom_signal_name miso_o role miso_o} spis1_miso_oe {direction Output atom_signal_name miso_oe role miso_oe} spis1_mosi_i {direction Input atom_signal_name mosi_i role mosi_i}} usb0_clk_in {usb0_ulpi_clk {direction Input atom_signal_name ulpi_clk role clk} @orderednames usb0_ulpi_clk} i2cemac2_scl_in {@orderednames i2c_emac2_scl_i i2c_emac2_scl_i {direction Input atom_signal_name scl_i role clk}} i2c0 {i2c0_sda_oe {direction Output atom_signal_name sda_oe role sda_oe} @orderednames {i2c0_sda_i i2c0_sda_oe} i2c0_sda_i {direction Input atom_signal_name sda_i role sda_i}} emac0_rx_clk_in {emac0_clk_rx_i {direction Input atom_signal_name clk_rx_i role clk} @orderednames emac0_clk_rx_i} i2c1 {i2c1_sda_oe {direction Output atom_signal_name sda_oe role sda_oe} @orderednames {i2c1_sda_i i2c1_sda_oe} i2c1_sda_i {direction Input atom_signal_name sda_i role sda_i}}} EMAC2_Mode N/A CLK_NOC_CNT 0 DB_periph_ifaces {@orderednames {CM EMAC0 EMAC1 EMAC2 NAND QSPI SDMMC USB0 USB1 SPIM0 SPIM1 SPIS0 SPIS1 TRACE UART0 UART1 I2C0 I2C1 I2CEMAC0 I2CEMAC1 I2CEMAC2} NAND {interfaces {nand {properties {} direction Input @no_export 0 type conduit} @orderednames nand} atom_name hps_interface_peripheral_nand} SPIM0 {interfaces {spim0_sclk_out {properties {} direction Output @no_export 0 type clock} @orderednames {spim0 spim0_sclk_out} spim0 {properties {} direction Input @no_export 0 type conduit}} atom_name hps_interface_peripheral_spi_master} USB0 {interfaces {usb0_clk_in {properties {} direction Input @no_export 0 type clock} @orderednames {usb0 usb0_clk_in} usb0 {properties {} direction Input @no_export 0 type conduit}} atom_name hps_interface_peripheral_usb} SPIM1 {interfaces {spim1_sclk_out {properties {} direction Output @no_export 0 type clock} @orderednames {spim1 spim1_sclk_out} spim1 {properties {} direction Input @no_export 0 type conduit}} atom_name hps_interface_peripheral_spi_master} USB1 {interfaces {@orderednames {usb1 usb1_clk_in} usb1_clk_in {properties {} direction Input @no_export 0 type clock} usb1 {properties {} direction Input @no_export 0 type conduit}} atom_name hps_interface_peripheral_usb} I2CEMAC0 {interfaces {i2cemac0 {properties {} direction Input @no_export 0 type conduit} @orderednames {i2cemac0_scl_in i2cemac0_clk i2cemac0} i2cemac0_clk {properties {} direction Output @no_export 0 type clock} i2cemac0_scl_in {properties {} direction Input @no_export 0 type clock}} atom_name hps_interface_peripheral_i2c} UART0 {interfaces {uart0 {properties {} direction Input @no_export 0 type conduit} @orderednames uart0} atom_name hps_interface_peripheral_uart} I2CEMAC1 {interfaces {i2cemac1_scl_in {properties {} direction Input @no_export 0 type clock} i2cemac1 {properties {} direction Input @no_export 0 type conduit} @orderednames {i2cemac1_scl_in i2cemac1_clk i2cemac1} i2cemac1_clk {properties {} direction Output @no_export 0 type clock}} atom_name hps_interface_peripheral_i2c} UART1 {interfaces {uart1 {properties {} direction Input @no_export 0 type conduit} @orderednames uart1} atom_name hps_interface_peripheral_uart} QSPI {interfaces {qspi_sclk_out {properties {} direction Output @no_export 0 type clock} qspi_s2f_clk {properties {} direction Output @no_export 0 type clock} qspi {properties {} direction Input @no_export 0 type conduit} @orderednames {qspi_sclk_out qspi_s2f_clk qspi}} atom_name hps_interface_peripheral_qspi} I2CEMAC2 {interfaces {i2cemac2_scl_in {properties {} direction Input @no_export 0 type clock} @orderednames {i2cemac2_scl_in i2cemac2_clk i2cemac2} i2cemac2 {properties {} direction Input @no_export 0 type conduit} i2cemac2_clk {properties {} direction Output @no_export 0 type clock}} atom_name hps_interface_peripheral_i2c} EMAC0 {interfaces {emac0_tx_clk_in {properties {} direction Input @no_export 0 type clock} emac0_rx_reset {properties {associatedClock emac0_rx_clk_in associatedResetSinks none} direction Output @no_export 0 type reset} emac0_gtx_clk {properties {} direction Output @no_export 0 type clock} @orderednames {emac0 emac0_md_clk emac0_rx_clk_in emac0_tx_clk_in emac0_gtx_clk emac0_tx_reset emac0_rx_reset} emac0_rx_clk_in {properties {} direction Input @no_export 0 type clock} emac0 {properties {} direction Input @no_export 0 type conduit} emac0_md_clk {properties {} direction Output @no_export 0 type clock} emac0_tx_reset {properties {associatedClock emac0_tx_clk_in associatedResetSinks none} direction Output @no_export 0 type reset}} atom_name hps_interface_peripheral_emac} TRACE {interfaces {@orderednames {trace_s2f_clk trace} trace_s2f_clk {properties {} direction Output @no_export 0 type clock} trace {properties {} direction Input @no_export 0 type conduit}} atom_name hps_interface_tpiu_trace} SPIS0 {interfaces {spis0_sclk_in {properties {} direction Input @no_export 0 type clock} @orderednames {spis0 spis0_sclk_in} spis0 {properties {} direction Input @no_export 0 type conduit}} atom_name hps_interface_peripheral_spi_slave} EMAC1 {interfaces {emac1_md_clk {properties {} direction Output @no_export 0 type clock} emac1_tx_reset {properties {associatedClock emac1_tx_clk_in associatedResetSinks none} direction Output @no_export 0 type reset} @orderednames {emac1 emac1_md_clk emac1_rx_clk_in emac1_tx_clk_in emac1_gtx_clk emac1_tx_reset emac1_rx_reset} emac1_tx_clk_in {properties {} direction Input @no_export 0 type clock} emac1_rx_reset {properties {associatedClock emac1_rx_clk_in associatedResetSinks none} direction Output @no_export 0 type reset} emac1_gtx_clk {properties {} direction Output @no_export 0 type clock} emac1_rx_clk_in {properties {} direction Input @no_export 0 type clock} emac1 {properties {} direction Input @no_export 0 type conduit}} atom_name hps_interface_peripheral_emac} SPIS1 {interfaces {spis1 {properties {} direction Input @no_export 0 type conduit} @orderednames {spis1 spis1_sclk_in} spis1_sclk_in {properties {} direction Input @no_export 0 type clock}} atom_name hps_interface_peripheral_spi_slave} CM {interfaces {cm {properties {} direction Input @no_export 0 type conduit} @orderednames cm}} EMAC2 {interfaces {emac2_rx_clk_in {properties {} direction Input @no_export 0 type clock} emac2 {properties {} direction Input @no_export 0 type conduit} @orderednames {emac2 emac2_md_clk emac2_rx_clk_in emac2_tx_clk_in emac2_gtx_clk emac2_tx_reset emac2_rx_reset} emac2_md_clk {properties {} direction Output @no_export 0 type clock} emac2_tx_reset {properties {associatedClock emac2_tx_clk_in associatedResetSinks none} direction Output @no_export 0 type reset} emac2_tx_clk_in {properties {} direction Input @no_export 0 type clock} emac2_rx_reset {properties {associatedClock emac2_rx_clk_in associatedResetSinks none} direction Output @no_export 0 type reset} emac2_gtx_clk {properties {} direction Output @no_export 0 type clock}} atom_name hps_interface_peripheral_emac} SDMMC {interfaces {sdmmc_cclk {properties {} direction Output @no_export 0 type clock} sdmmc {properties {} direction Input @no_export 0 type conduit} @orderednames {sdmmc sdmmc_reset sdmmc_clk_in sdmmc_cclk} sdmmc_reset {properties {synchronousEdges none} direction Output @no_export 0 type reset} sdmmc_clk_in {properties {} direction Input @no_export 0 type clock}} atom_name hps_interface_peripheral_sdmmc} I2C0 {interfaces {i2c0_scl_in {properties {} direction Input @no_export 0 type clock} @orderednames {i2c0_scl_in i2c0_clk i2c0} i2c0 {properties {} direction Input @no_export 0 type conduit} i2c0_clk {properties {} direction Output @no_export 0 type clock}} atom_name hps_interface_peripheral_i2c} I2C1 {interfaces {i2c1_clk {properties {} direction Output @no_export 0 type clock} @orderednames {i2c1_scl_in i2c1_clk i2c1} i2c1_scl_in {properties {} direction Input @no_export 0 type clock} i2c1 {properties {} direction Input @no_export 0 type conduit}} atom_name hps_interface_peripheral_i2c}} NOCDIV_L4SPCLK 2 SDMMC_Mode N/A UART0_PinMuxing Unused F2S_Width 6 dev_database {} FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM1_SCLK_OUT 100 S2FINTERRUPT_FPGAMANAGER_Enable false F2H_SDRAM0_CLOCK_FREQ 100 NOCDIV_CS_ATCLK 0 EMAC2_SWITCH_Enable false CLK_MPU_CNT 0 S2FINTERRUPT_USB1_Enable false SDMMC_PinMuxing Unused CLK_S2F_USER0_SOURCE 0 MAINPLLGRP_S2F_USER0_CNT 900 DB_port_pins {spim0_miso_i {0 rxd} usb0_ulpi_stp {0 ulpi_stp} emac0_ptp_aux_ts_trig_i {0 ts_trig} uart1_dsr_n {0 dsr_n} spim0_ss1_n_o {0 ss_cs1} qspi_io0_o {0 mo0} emac1_ptp_pps_o {0 ptp_pps} emac1_phy_txclk_o {0 tx_clk_o} spim1_ss1_n_o {0 ss_cs1} sdmmc_clk_in {0 clk_in} emac0_phy_rxd_i {0 rxd0 4 rxd4 5 rxd5 1 rxd1 2 rxd2 6 rxd6 7 rxd7 3 rxd3} emac1_ptp_tstmp_en {0 ptp_tstmp_en} emac1_clk_tx_i {0 tx_clk_i} uart1_dcd_n {0 dcd_n} spim0_ss3_n_o {0 ss_cs3} spim0_sclk_out {0 sclk_out} spis1_miso_o {0 txd} spim1_ss3_n_o {0 ss_cs3} emac1_gmii_mdi_i {0 mdi} emac0_phy_rxer_i {0 rxer} emac1_rst_clk_tx_n_o {0 rst_clk_tx_n_o} emac0_clk_rx_i {0 rx_clk} uart0_rts_n {0 rts_n} spis0_sclk_in {0 sclk_in} trace_s2f_clk {0 s2f_clk} i2c_emac0_sda_i {0 ic_data_in_a} spis1_sclk_in {0 sclk_in} usb1_ulpi_stp {0 ulpi_stp} emac2_gmii_mdo_o {0 mdo} emac1_phy_rxdv_i {0 rxdv} i2c1_scl_oe {0 ic_clk_oe} uart1_cts_n {0 cts_n} emac0_phy_txd_o {0 txd0 4 txd4 5 txd5 1 txd1 2 txd2 6 txd6 7 txd7 3 txd3} uart1_ri_n {0 ri_n} spis0_miso_o {0 txd} emac2_clk_tx_i {0 tx_clk_i} emac0_gmii_mdc_o {0 mdc} emac1_phy_col_i {0 col} emac2_phy_txen_o {0 txen} uart0_rx {0 sin} spim1_sclk_out {0 sclk_out} qspi_io1_i {0 mi1} emac0_rst_clk_tx_n_o {0 rst_clk_tx_n_o} i2c_emac2_scl_i {0 ic_clk_in_a} i2c1_sda_i {0 ic_data_in_a} emac1_phy_crs_i {0 crs} usb0_ulpi_data_oe {0 ulpi_data_out_en0 4 ulpi_data_out_en4 5 ulpi_data_out_en5 1 ulpi_data_out_en1 2 ulpi_data_out_en2 6 ulpi_data_out_en6 7 ulpi_data_out_en7 3 ulpi_data_out_en3} sdmmc_cmd_i {0 ccmd_i} emac2_phy_txer_o {0 txer} uart0_dsr_n {0 dsr_n} spis0_miso_oe {0 ssi_oe_n} emac1_clk_rx_i {0 rx_clk} i2c0_scl_oe {0 ic_clk_oe} spis1_miso_oe {0 ssi_oe_n} emac1_ptp_aux_ts_trig_i {0 ts_trig} uart0_dcd_n {0 dcd_n} qspi_io1_o {0 mo1} emac2_ptp_pps_o {0 ptp_pps} usb0_ulpi_data_i {0 ulpi_datain0 4 ulpi_datain4 5 ulpi_datain5 1 ulpi_datain1 2 ulpi_datain2 6 ulpi_datain6 7 ulpi_datain7 3 ulpi_datain3} usb0_ulpi_nxt {0 ulpi_nxt} emac0_gmii_mdo_o_e {0 mdo_en} emac0_phy_mac_speed_o {0 mac_speed0 1 mac_speed1} emac1_phy_rxd_i {0 rxd0 4 rxd4 5 rxd5 1 rxd1 2 rxd2 6 rxd6 7 rxd7 3 rxd3} sdmmc_cmd_o {0 ccmd_o} sdmmc_card_intn_i {0 card_int_n} sdmmc_pwr_ena_o {0 pwer_en_o} emac1_phy_mac_speed_o {0 mac_speed0 1 mac_speed1} emac2_phy_mac_speed_o {0 mac_speed0 1 mac_speed1} sdmmc_cclk_out {0 cclk_out} sdmmc_rstn_o {0 rst_out_n} sdmmc_cdn_i {0 cd_i_n} emac0_gmii_mdo_o {0 mdo} i2c_emac2_scl_oe {0 ic_clk_oe} i2c1_sda_oe {0 ic_data_oe} uart0_cts_n {0 cts_n} usb0_ulpi_data_o {0 ulpi_dataout0 4 ulpi_dataout4 5 ulpi_dataout5 1 ulpi_dataout1 2 ulpi_dataout2 6 ulpi_dataout6 7 ulpi_dataout7 3 ulpi_dataout3} sdmmc_vs_o {0 vs_o} emac2_clk_rx_i {0 rx_clk} emac0_phy_txen_o {0 txen} emac0_ptp_tstmp_en {0 ptp_tstmp_en} uart1_dtr_n {0 dtr_n} emac1_phy_txd_o {0 txd0 4 txd4 5 txd5 1 txd1 2 txd2 6 txd6 7 txd7 3 txd3} i2c_emac1_scl_i {0 ic_clk_in_a} i2c0_sda_i {0 ic_data_in_a} usb1_ulpi_nxt {0 ulpi_nxt} emac2_phy_col_i {0 col} qspi_io2_i {0 mi2} nand_adq_i {0 adq_in0 1 adq_in1 2 adq_in2 3 adq_in3 4 adq_in4 5 adq_in5 6 adq_in6 7 adq_in7 8 adq_in8 10 adq_in10 9 adq_in9 11 adq_in11 12 adq_in12 13 adq_in13 14 adq_in14 15 adq_in15} emac2_gmii_mdi_i {0 mdi} emac0_phy_txer_o {0 txer} uart0_tx {0 sout} spis1_mosi_i {0 rxd} spis0_ss_in_n {0 ss_in_n} spim1_mosi_o {0 txd} emac2_phy_crs_i {0 crs} emac1_phy_rxer_i {0 rxer} i2c_emac1_scl_oe {0 ic_clk_oe} i2c0_sda_oe {0 ic_data_oe} spis1_ss_in_n {0 ss_in_n} nand_ale_o {0 ale_out} spim0_ss0_n_o {0 ss_cs0} usb0_ulpi_dir {0 ulpi_dir} emac0_phy_txclk_o {0 tx_clk_o} uart1_out1_n {0 out1_n} spim1_ss0_n_o {0 ss_cs0} sdmmc_cmd_oe {0 ccmd_en} nand_cle_o {0 cle_out} uart0_ri_n {0 ri_n} spim0_ss2_n_o {0 ss_cs2} qspi_io3_hold_o {0 mo3_hold} emac2_phy_txclk_o {0 tx_clk_o} emac2_ptp_aux_ts_trig_i {0 ts_trig} emac2_phy_rxdv_i {0 rxdv} spim1_ss2_n_o {0 ss_cs2} usb0_ulpi_clk {0 ulpi_clk} nand_adq_o {0 adq_out0 1 adq_out1 2 adq_out2 3 adq_out3 4 adq_out4 5 adq_out5 6 adq_out6 7 adq_out7 8 adq_out8 10 adq_out10 9 adq_out9 11 adq_out11 12 adq_out12 13 adq_out13 14 adq_out14 15 adq_out15} sdmmc_data_i {0 cdata_in0 4 cdata_in4 5 cdata_in5 1 cdata_in1 2 cdata_in2 6 cdata_in6 7 cdata_in7 3 cdata_in3} emac2_phy_rxd_i {0 rxd0 4 rxd4 5 rxd5 1 rxd1 2 rxd2 6 rxd6 7 rxd7 3 rxd3} emac1_gmii_mdc_o {0 mdc} uart1_rx {0 sin} spis0_mosi_i {0 rxd} spim0_mosi_o {0 txd} emac2_gmii_mdo_o_e {0 mdo_en} i2c_emac2_sda_oe {0 ic_data_oe} i2c_emac0_scl_oe {0 ic_clk_oe} trace_data {17 d17 0 d0 18 d18 1 d1 20 d20 19 d19 2 d2 21 d21 3 d3 22 d22 4 d4 23 d23 5 d5 6 d6 24 d24 25 d25 7 d7 8 d8 26 d26 27 d27 9 d9 10 d10 11 d11 28 d28 29 d29 12 d12 30 d30 31 d31 13 d13 14 d14 15 d15 16 d16} sdmmc_data_oe {0 cdata_out_en0 4 cdata_out_en4 5 cdata_out_en5 1 cdata_out_en1 2 cdata_out_en2 6 cdata_out_en6 7 cdata_out_en7 3 cdata_out_en3} qspi_s2f_clk {0 s2f_clk} qspi_sclk_out {0 sck_out} uart0_out1_n {0 out1_n} spim0_ss_in_n {0 ss_in_n} nand_rdy_busy_i {0 rdy_bsy_in0 1 rdy_bsy_in1 2 rdy_bsy_in2 3 rdy_bsy_in3} nand_adq_oe {0 adq_oe0} uart0_dtr_n {0 dtr_n} spim1_ss_in_n {0 ss_in_n} usb1_ulpi_dir {0 ulpi_dir} sdmmc_data_o {0 cdata_out0 4 cdata_out4 5 cdata_out5 1 cdata_out1 2 cdata_out2 6 cdata_out6 7 cdata_out7 3 cdata_out3} qspi_mo_oe {0 n_mo_en0 1 n_mo_en1 2 n_mo_en2 3 n_mo_en3} emac2_ptp_tstmp_data {0 ptp_tstmp_data} i2c_emac2_sda_i {0 ic_data_in_a} i2c_emac0_scl_i {0 ic_clk_in_a} emac2_ptp_tstmp_en {0 ptp_tstmp_en} emac0_gmii_mdi_i {0 mdi} usb1_ulpi_clk {0 ulpi_clk} nand_wp_o {0 wp_outn} emac2_rst_clk_rx_n_o {0 rst_clk_rx_n_o} emac2_phy_txd_o {0 txd0 4 txd4 5 txd5 1 txd1 2 txd2 6 txd6 7 txd7 3 txd3} i2c_emac1_sda_oe {0 ic_data_oe} qspi_io3_i {0 mi3} i2c1_scl_i {0 ic_clk_in_a} qspi_ss_o {0 n_ss_out0 1 n_ss_out1 2 n_ss_out2 3 n_ss_out3} qspi_io2_wpn_o {0 mo2_wpn} emac0_phy_rxdv_i {0 rxdv} emac0_ptp_pps_o {0 ptp_pps} emac1_gmii_mdo_o {0 mdo} trace_clk_ctl {0 clk_ctl} nand_we_o {0 we_outn} emac1_ptp_tstmp_data {0 ptp_tstmp_data} uart1_out2_n {0 out2_n} emac1_phy_txen_o {0 txen} emac1_rst_clk_rx_n_o {0 rst_clk_rx_n_o} i2c_emac0_sda_oe {0 ic_data_oe} usb1_ulpi_data_i {0 ulpi_datain0 4 ulpi_datain4 5 ulpi_datain5 1 ulpi_datain1 2 ulpi_datain2 6 ulpi_datain6 7 ulpi_datain7 3 ulpi_datain3} nand_re_o {0 re_outn} trace_clkin {0 clkin} emac1_phy_txer_o {0 txer} uart1_tx {0 sout} usb1_ulpi_data_oe {0 ulpi_data_out_en0 4 ulpi_data_out_en4 5 ulpi_data_out_en5 1 ulpi_data_out_en1 2 ulpi_data_out_en2 6 ulpi_data_out_en6 7 ulpi_data_out_en7 3 ulpi_data_out_en3} emac2_phy_rxer_i {0 rxer} spim1_miso_i {0 rxd} emac0_ptp_tstmp_data {0 ptp_tstmp_data} uart1_rts_n {0 rts_n} uart0_out2_n {0 out2_n} sdmmc_wp_i {0 wp_i} emac0_clk_tx_i {0 tx_clk_i} i2c_emac1_sda_i {0 ic_data_in_a} spim0_mosi_oe {0 ssi_oe_n} usb1_ulpi_data_o {0 ulpi_dataout0 4 ulpi_dataout4 5 ulpi_dataout5 1 ulpi_dataout1 2 ulpi_dataout2 6 ulpi_dataout6 7 ulpi_dataout7 3 ulpi_dataout3} emac0_phy_col_i {0 col} emac0_rst_clk_rx_n_o {0 rst_clk_rx_n_o} spim1_mosi_oe {0 ssi_oe_n} qspi_io0_i {0 mi0} emac0_phy_crs_i {0 crs} emac1_gmii_mdo_o_e {0 mdo_en} nand_ce_o {0 ce_outn0 1 ce_outn1 2 ce_outn2 3 ce_outn3} emac2_gmii_mdc_o {0 mdc} i2c0_scl_i {0 ic_clk_in_a} emac2_rst_clk_tx_n_o {0 rst_clk_tx_n_o}} quartus_ini_hps_ip_boot_from_fpga_ready false MAINPLLGRP_GPIO_DB_CNT 900 MAINPLLGRP_VCO_DENOM 1 USB0_PinMuxing IO S2F_Width 4 TRACE_Mode default I2CEMAC2_PinMuxing Unused S2FINTERRUPT_I2C1_Enable false FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2CEMAC2_SCL_IN 100 S2FINTERRUPT_CLOCKPERIPHERAL_Enable false FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC0_RX_CLK_IN 100 DEFAULT_MPU_CLK 1200 H2F_COLD_RST_Enable false FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC2_MD_CLK 2.5 MAINPLLGRP_EMACB_CNT 900 S2FINTERRUPT_I2CEMAC1_Enable false FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_GTX_CLK 125 MAINPLLGRP_EMAC_PTP_CNT 900 PERI_PLL_AUTO_VCO_FREQ 2000 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C0_SCL_IN 100 F2H_SDRAM1_CLOCK_FREQ 100 EMAC0_CLK 250 DMA_PeriphId_DERIVED {0 1 2 3 4 5 6 7} BOOT_FROM_FPGA_Enable false FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2CEMAC0_SCL_IN 100 PERPLLGRP_NOC_CNT 900 Quad_4_Save {} PERPLLGRP_HMC_PLL_REF_CNT 900 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_MD_CLK 2.5 DMA_Enable {No No No No No No No No} FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC1_TX_CLK_IN 100 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C1_CLK 100 Quad_1_Save {} EMAC1_PTP false eosc1_clk_mhz 25.0 F2H_DBG_RST_Enable true PERPLLGRP_MPU_CNT 900 F2SDRAM2_DELAY 4 S2FINTERRUPT_GPIO_Enable false H2F_USER0_CLK_FREQ 400 H2F_USER0_CLK_Enable false FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC2_RX_CLK_IN 100 UART0_Mode N/A F2H_SDRAM2_CLOCK_FREQ 100 NOCDIV_L4MPCLK 0 H2F_PENDING_RST_Enable false I2C0_PinMuxing Unused S2FINTERRUPT_SPIS1_Enable false S2FINTERRUPT_SPIM0_Enable false FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2CEMAC1_CLK 100 USB1_Mode N/A S2FINTERRUPT_DMA_Enable false H2F_CTI_CLOCK_FREQ 100 SPIM1_PinMuxing IO QSPI_Mode 1ss F2SDRAM0_ENABLED true CLK_EMACB_SOURCE 1 SPIS0_Mode N/A MAINPLLGRP_VCO_NUMER 191 EMAC0_PinMuxing IO SPIS0_PinMuxing Unused PERPLLGRP_S2F_USER1_CNT 900 CM_PinMuxing Unused SPIM1_Mode Dual_slave_selects FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC_PTP_REF_CLOCK 100 PERPLLGRP_SDMMC_CNT 900 S2FINTERRUPT_UART0_Enable false TESTIOCTRL_PERICLKSEL 8 pin_muxing_check {} SECURITY_MODULE_Enable false S2FINTERRUPT_EMAC2_Enable false S2FINTERRUPT_SYSTIMER_Enable false quartus_ini_hps_ip_enable_sdmmc_clk_in false H2F_USER1_CLK_Enable false RUN_INTERNAL_BUILD_CHECKS 0 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_USB0_CLK_IN 100 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SPIS0_SCLK_IN 100 I2CEMAC1_Mode N/A F2H_AXI_CLOCK_FREQ 100000000 F2H_SDRAM3_CLOCK_FREQ 100 CLK_NOC_SOURCE 0 TESTIOCTRL_DEBUGCLKSEL 16 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SDMMC_CLK_IN 100 MPU_CLK_VCCL 1 EMAC1_Mode N/A USE_DEFAULT_MPU_CLK false S2FINTERRUPT_HMC_Enable false GP_Enable false eosc1_clk_hz 0 S2FINTERRUPT_EMAC0_Enable false FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC2_GTX_CLK 125 MAINPLLGRP_PERIPH_REF_CNT 900 H2F_DELAY 3 quartus_ini_hps_ip_overide_f2sdram_delay false NAND_PinMuxing Unused FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_QSPI_SCLK_OUT 100 EMAC2_CLK 250 GPIO_REF_CLK 4 OVERIDE_PERI_PLL false PERPLLGRP_EMAC_PTP_CNT 19 EMAC2_PinMuxing Unused DEBUG_APB_Enable false EMIF_BYPASS_CHECK false F2SDRAM_PORT_CONFIG 6 F2H_FREE_CLK_Enable false PERPLLGRP_VCO_DENOM 1 F2H_SDRAM4_CLOCK_FREQ 100 JTAG_Enable false EMAC2SEL 0 MAINPLLGRP_HMC_PLL_REF_CNT 900 CTI_Enable false BSEL_EN false SDMMC_REF_CLK 200 H2F_LW_AXI_CLOCK_FREQ 100000000 PERPLLGRP_EMACB_CNT 900 F2H_FREE_CLK_FREQ 200 F2H_COLD_RST_Enable true MAINPLLGRP_EMACA_CNT 900 Quad_3_Save {} H2F_USER1_CLK_FREQ 400 L4_SYS_FREE_CLK 1 LWH2F_Enable 2 F2SDRAM1_ENABLED false I2CEMAC1_PinMuxing Unused F2H_SDRAM5_CLOCK_FREQ 100 CLK_S2F_USER1_SOURCE 0 S2FINTERRUPT_CTI_Enable false TEST_Enable false NOCDIV_CS_PDBGCLK 1 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C0_CLK 100 PERPLLGRP_GPIO_DB_CNT 499 NOCDIV_CS_TRACECLK 1 HPS_DIV_GPIO_FREQ 125 CLK_GPIO_SOURCE 1 EMAC0_PTP false NOCDIV_L4MAINCLK 0 I2C1_Mode default S2FINTERRUPT_SYSTEMMANAGER_Enable false S2FINTERRUPT_USB0_Enable false PIN_TO_BALL_MAP {Q2_1 H18 Q2_2 H19 Q2_3 F18 Q2_4 G17 Q2_5 E20 Q2_6 F20 Q2_7 G20 Q2_8 G21 Q2_10 G19 Q2_9 F19 Q2_11 F22 Q2_12 G22 D_4 E16 D_5 H16 D_6 K16 D_7 G16 D_8 H17 D_9 F15 Q3_1 K18 Q3_2 L19 Q3_3 H22 Q3_4 H21 Q3_5 J21 Q3_6 J20 Q3_7 J18 Q3_8 J19 D_10 L17 Q3_9 H23 D_11 N19 D_12 M19 D_13 E15 D_14 J16 D_15 L18 D_16 M17 D_17 K17 Q3_10 J23 Q4_1 L20 Q3_11 K21 Q4_2 M20 Q3_12 K20 Q4_3 N20 Q4_4 P20 Q4_5 K23 Q4_6 L23 Q4_7 N23 Q4_8 N22 Q4_9 K22 Q1_10 D20 Q1_1 D18 Q1_11 E21 Q1_2 E18 Q1_12 E22 Q1_3 C19 Q1_4 D19 Q1_5 E17 Q1_6 F17 Q1_7 C17 Q1_8 C18 Q1_9 D21 Q4_10 L22 Q4_11 M22 Q4_12 M21} HPS_IO_Enable {QSPI:CLK QSPI:IO0 QSPI:SS0 QSPI:IO1 QSPI:IO2_WPN QSPI:IO3_HOLD NONE NONE NONE NONE NONE NONE UART1:TX UART1:RX USB0:CLK USB0:STP USB0:DIR USB0:DATA0 USB0:DATA1 USB0:NXT USB0:DATA2 USB0:DATA3 USB0:DATA4 USB0:DATA5 USB0:DATA6 USB0:DATA7 EMAC0:TX_CLK EMAC0:TX_CTL EMAC0:RX_CLK EMAC0:RX_CTL EMAC0:TXD0 EMAC0:TXD1 EMAC0:RXD0 EMAC0:RXD1 EMAC0:TXD2 EMAC0:TXD3 EMAC0:RXD2 EMAC0:RXD3 SPIM1:CLK SPIM1:MOSI SPIM1:MISO SPIM1:SS0_N SPIM1:SS1_N GPIO NONE NONE NONE NONE MDIO0:MDIO MDIO0:MDC I2C1:SDA I2C1:SCL GPIO TRACE:CLK GPIO GPIO NONE NONE TRACE:D0 TRACE:D1 TRACE:D2 TRACE:D3} CLK_HMC_PLL_SOURCE 0 S2FINTERRUPT_SDMMC_Enable false FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SPIS1_SCLK_IN 100 UART1_PinMuxing IO S2FINTERRUPT_I2CEMAC2_Enable false F2SDRAM_ADDRESS_WIDTH 32 EMAC1SEL 0 HMC_PLL_REF_CLK 800 TRACE_PinMuxing IO FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C1_SCL_IN 100 USB0_Mode default FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC0_TX_CLK_IN 100 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SDMMC_CCLK 100 DISABLE_PERI_PLL false CLK_PERI_PLL_SOURCE2 0 S2FINTERRUPT_I2C0_Enable false FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2CEMAC1_SCL_IN 100 EMIF_CONDUIT_Enable true SPIM0_Mode N/A FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2CEMAC0_CLK 100 PERPLLGRP_VCO_NUMER 159 S2FINTERRUPT_L4TIMER_Enable false H2F_TPIU_CLOCK_IN_FREQ 100 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_MD_CLK 2.5 USB1_PinMuxing Unused S2FINTERRUPT_I2CEMAC0_Enable false F2SDRAM_READY_LATENCY true PERPLLGRP_S2F_USER0_CNT 900 EMAC0_SWITCH_Enable false S2FINTERRUPT_WATCHDOG_Enable false FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC1_RX_CLK_IN 100 I2CEMAC0_Mode N/A EMAC0_Mode RGMII_with_MDIO S2FINTERRUPT_QSPI_Enable false MAINPLLGRP_S2F_USER1_CNT 900 pin_muxing {} INTERNAL_OSCILLATOR_ENABLE 60 SPIM0_PinMuxing Unused PERI_PLL_MANUAL_VCO_FREQ 2000 F2H_WARM_RST_Enable true CUSTOM_MPU_CLK 1020 L3_MAIN_FREE_CLK 200 F2SINTERRUPT_Enable true S2FINTERRUPT_SPIM1_Enable false device_name 10AS066N3F40E2SG FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC2_TX_CLK_IN 100 EMAC0SEL 0 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM0_SCLK_OUT 100 F2H_DELAY 3 CONFIG_HPS_DIV_GPIO 32000 EMAC1_CLK 250 S2FINTERRUPT_UART1_Enable false F2SDRAM2_ENABLED true MPU_EVENTS_Enable false S2FINTERRUPT_SPIS0_Enable false EMAC_PTP_REF_CLK 100 CLK_EMACA_SOURCE 1 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_USB1_CLK_IN 100 hps_device_family {Arria 10} EMAC2_PTP false CLK_MPU_SOURCE 0 I2C1_PinMuxing IO NAND_Mode N/A H2F_LW_DELAY 3 quartus_ini_hps_ip_override_sdmmc_4bit false Quad_2_Save {} PERPLLGRP_EMACA_CNT 7 S2FINTERRUPT_EMAC1_Enable false EMAC1_PinMuxing Unused SPIS1_PinMuxing Unused EMAC1_SWITCH_Enable false BSEL 1 PLL_CLK0 Unused FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_GTX_CLK 100 PLL_CLK1 Unused quartus_ini_hps_ip_enable_test_interface false PLL_CLK2 Unused PLL_CLK3 Unused CM_Mode N/A PLL_CLK4 Unused FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2CEMAC2_CLK 100 CLK_MAIN_PLL_SOURCE2 0 TESTIOCTRL_MAINCLKSEL 8 UART1_Mode No_flow_control I2C0_Mode N/A STM_Enable true generateLegacySim false

  

Software Assignments (none)

---

a10_hps_clk_0

hps_clk_src v19.1

Parameters deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

a10_hps_bridges

arria10_hps_bridge_avalon v19.1

Parameters address_map <address-map><slave name='i_emac_emac0.axi_slave0' start='0xFF800000' end='0xFF802000' datawidth='32' /><slave name='i_emac_emac1.axi_slave0' start='0xFF802000' end='0xFF804000' datawidth='32' /><slave name='i_emac_emac2.axi_slave0' start='0xFF804000' end='0xFF806000' datawidth='32' /><slave name='i_sdmmc_sdmmc.axi_slave0' start='0xFF808000' end='0xFF809000' datawidth='32' /><slave name='i_qspi_QSPIDATA.axi_slave0' start='0xFF809000' end='0xFF809100' datawidth='32' /><slave name='i_qspi_QSPIDATA.axi_slave1' start='0xFFA00000' end='0xFFA00100' datawidth='32' /><slave name='i_usbotg_0_globgrp.axi_slave0' start='0xFFB00000' end='0xFFB40000' datawidth='32' /><slave name='i_usbotg_1_globgrp.axi_slave0' start='0xFFB40000' end='0xFFB80000' datawidth='32' /><slave name='i_nand_NANDDATA.axi_slave1' start='0xFFB80000' end='0xFFB90000' datawidth='32' /><slave name='i_nand_NANDDATA.axi_slave0' start='0xFFB90000' end='0xFFBA0000' datawidth='32' /><slave name='i_uart_0_uart.axi_slave0' start='0xFFC02000' end='0xFFC02100' datawidth='32' /><slave name='i_uart_1_uart.axi_slave0' start='0xFFC02100' end='0xFFC02200' datawidth='32' /><slave name='i_i2c_0_i2c.axi_slave0' start='0xFFC02200' end='0xFFC02300' datawidth='32' /><slave name='i_i2c_1_i2c.axi_slave0' start='0xFFC02300' end='0xFFC02400' datawidth='32' /><slave name='i_i2c_emac_0_i2c.axi_slave0' start='0xFFC02400' end='0xFFC02500' datawidth='32' /><slave name='i_i2c_emac_1_i2c.axi_slave0' start='0xFFC02500' end='0xFFC02600' datawidth='32' /><slave name='i_i2c_emac_2_i2c.axi_slave0' start='0xFFC02600' end='0xFFC02700' datawidth='32' /><slave name='i_timer_sp_0_timer.axi_slave0' start='0xFFC02700' end='0xFFC02800' datawidth='32' /><slave name='i_timer_sp_1_timer.axi_slave0' start='0xFFC02800' end='0xFFC02900' datawidth='32' /><slave name='i_gpio_0_gpio.axi_slave0' start='0xFFC02900' end='0xFFC02A00' datawidth='32' /><slave name='i_gpio_1_gpio.axi_slave0' start='0xFFC02A00' end='0xFFC02B00' datawidth='32' /><slave name='i_gpio_2_gpio.axi_slave0' start='0xFFC02B00' end='0xFFC02C00' datawidth='32' /><slave name='i_fpga_mgr_fpgamgrregs.axi_slave1' start='0xFFCFE400' end='0xFFCFE500' datawidth='32' /><slave name='i_timer_sys_0_timer.axi_slave0' start='0xFFD00000' end='0xFFD00100' datawidth='32' /><slave name='i_timer_sys_1_timer.axi_slave0' start='0xFFD00100' end='0xFFD00200' datawidth='32' /><slave name='i_watchdog_0_l4wd.axi_slave0' start='0xFFD00200' end='0xFFD00300' datawidth='32' /><slave name='i_watchdog_1_l4wd.axi_slave0' start='0xFFD00300' end='0xFFD00400' datawidth='32' /><slave name='i_fpga_mgr_fpgamgrregs.axi_slave0' start='0xFFD03000' end='0xFFD04000' datawidth='32' /><slave name='baum_clkmgr.axi_slave0' start='0xFFD04000' end='0xFFD05000' datawidth='32' /><slave name='i_rst_mgr_rstmgr.axi_slave0' start='0xFFD05000' end='0xFFD05100' datawidth='32' /><slave name='i_sys_mgr_core.axi_slave0' start='0xFFD06000' end='0xFFD06400' datawidth='32' /><slave name='i_dma_DMASECURE.axi_slave0' start='0xFFDA1000' end='0xFFDA2000' datawidth='32' /><slave name='i_spim_0_spim.axi_slave0' start='0xFFDA4000' end='0xFFDA4100' datawidth='32' /><slave name='i_spim_1_spim.axi_slave0' start='0xFFDA5000' end='0xFFDA5100' datawidth='32' /><slave name='arm_gic_0.axi_slave1' start='0xFFFFC100' end='0xFFFFC200' datawidth='32' /><slave name='arm_gic_0.axi_slave0' start='0xFFFFD000' end='0xFFFFE000' datawidth='32' /><slave name='mpu_reg_l2_MPUL2.axi_slave0' start='0xFFFFF000' end='0x100000000' datawidth='32' /></address-map> F2S_Width 6 S2F_Width 4 LWH2F_Enable 2 F2SDRAM_PORT_CONFIG 6 F2SDRAM0_ENABLED true F2SDRAM1_ENABLED false F2SDRAM2_ENABLED true F2SDRAM_READY_LATENCY true F2SDRAM_ADDRESS_WIDTH 32 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

a10_hps_eosc1

hps_virt_clk v19.1

Parameters clockFrequency 25000000 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

a10_hps_cb_intosc_hs_div2_clk

hps_virt_clk v19.1

Parameters clockFrequency 0 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

a10_hps_cb_intosc_ls_clk

hps_virt_clk v19.1

Parameters clockFrequency 60000000 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

a10_hps_f2s_free_clk

hps_virt_clk v19.1

Parameters clockFrequency 200000000 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

a10_hps_arm_a9_0

arm_a9 v19.1

Parameters address_map <address-map><slave name='bridges.axi_h2f' start='0xC0000000' end='0xE0000000' datawidth='32' /><slave name='bridges.axi_h2f_lw' start='0xFF200000' end='0xFF400000' datawidth='32' /><slave name='i_emac_emac0.axi_slave0' start='0xFF800000' end='0xFF802000' datawidth='32' /><slave name='i_emac_emac1.axi_slave0' start='0xFF802000' end='0xFF804000' datawidth='32' /><slave name='i_emac_emac2.axi_slave0' start='0xFF804000' end='0xFF806000' datawidth='32' /><slave name='i_sdmmc_sdmmc.axi_slave0' start='0xFF808000' end='0xFF809000' datawidth='32' /><slave name='i_qspi_QSPIDATA.axi_slave0' start='0xFF809000' end='0xFF809100' datawidth='32' /><slave name='i_qspi_QSPIDATA.axi_slave1' start='0xFFA00000' end='0xFFA00100' datawidth='32' /><slave name='i_usbotg_0_globgrp.axi_slave0' start='0xFFB00000' end='0xFFB40000' datawidth='32' /><slave name='i_usbotg_1_globgrp.axi_slave0' start='0xFFB40000' end='0xFFB80000' datawidth='32' /><slave name='i_nand_NANDDATA.axi_slave1' start='0xFFB80000' end='0xFFB90000' datawidth='32' /><slave name='i_nand_NANDDATA.axi_slave0' start='0xFFB90000' end='0xFFBA0000' datawidth='32' /><slave name='i_uart_0_uart.axi_slave0' start='0xFFC02000' end='0xFFC02100' datawidth='32' /><slave name='i_uart_1_uart.axi_slave0' start='0xFFC02100' end='0xFFC02200' datawidth='32' /><slave name='i_i2c_0_i2c.axi_slave0' start='0xFFC02200' end='0xFFC02300' datawidth='32' /><slave name='i_i2c_1_i2c.axi_slave0' start='0xFFC02300' end='0xFFC02400' datawidth='32' /><slave name='i_i2c_emac_0_i2c.axi_slave0' start='0xFFC02400' end='0xFFC02500' datawidth='32' /><slave name='i_i2c_emac_1_i2c.axi_slave0' start='0xFFC02500' end='0xFFC02600' datawidth='32' /><slave name='i_i2c_emac_2_i2c.axi_slave0' start='0xFFC02600' end='0xFFC02700' datawidth='32' /><slave name='i_timer_sp_0_timer.axi_slave0' start='0xFFC02700' end='0xFFC02800' datawidth='32' /><slave name='i_timer_sp_1_timer.axi_slave0' start='0xFFC02800' end='0xFFC02900' datawidth='32' /><slave name='i_gpio_0_gpio.axi_slave0' start='0xFFC02900' end='0xFFC02A00' datawidth='32' /><slave name='i_gpio_1_gpio.axi_slave0' start='0xFFC02A00' end='0xFFC02B00' datawidth='32' /><slave name='i_gpio_2_gpio.axi_slave0' start='0xFFC02B00' end='0xFFC02C00' datawidth='32' /><slave name='i_fpga_mgr_fpgamgrregs.axi_slave1' start='0xFFCFE400' end='0xFFCFE500' datawidth='32' /><slave name='i_timer_sys_0_timer.axi_slave0' start='0xFFD00000' end='0xFFD00100' datawidth='32' /><slave name='i_timer_sys_1_timer.axi_slave0' start='0xFFD00100' end='0xFFD00200' datawidth='32' /><slave name='i_watchdog_0_l4wd.axi_slave0' start='0xFFD00200' end='0xFFD00300' datawidth='32' /><slave name='i_watchdog_1_l4wd.axi_slave0' start='0xFFD00300' end='0xFFD00400' datawidth='32' /><slave name='i_fpga_mgr_fpgamgrregs.axi_slave0' start='0xFFD03000' end='0xFFD04000' datawidth='32' /><slave name='baum_clkmgr.axi_slave0' start='0xFFD04000' end='0xFFD05000' datawidth='32' /><slave name='i_rst_mgr_rstmgr.axi_slave0' start='0xFFD05000' end='0xFFD05100' datawidth='32' /><slave name='i_sys_mgr_core.axi_slave0' start='0xFFD06000' end='0xFFD06400' datawidth='32' /><slave name='i_dma_DMASECURE.axi_slave0' start='0xFFDA1000' end='0xFFDA2000' datawidth='32' /><slave name='i_spis_0_spis.axi_slave0' start='0xFFDA2000' end='0xFFDA2100' datawidth='32' /><slave name='i_spis_1_spis.axi_slave0' start='0xFFDA3000' end='0xFFDA3100' datawidth='32' /><slave name='i_spim_0_spim.axi_slave0' start='0xFFDA4000' end='0xFFDA4100' datawidth='32' /><slave name='i_spim_1_spim.axi_slave0' start='0xFFDA5000' end='0xFFDA5100' datawidth='32' /><slave name='scu.axi_slave0' start='0xFFFFC000' end='0xFFFFC100' datawidth='32' /><slave name='arm_gic_0.axi_slave1' start='0xFFFFC100' end='0xFFFFC200' datawidth='32' /><slave name='timer.axi_slave0' start='0xFFFFC600' end='0xFFFFC700' datawidth='32' /><slave name='arm_gic_0.axi_slave0' start='0xFFFFD000' end='0xFFFFE000' datawidth='32' /><slave name='mpu_reg_l2_MPUL2.axi_slave0' start='0xFFFFF000' end='0x100000000' datawidth='32' /></address-map> deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

a10_hps_arm_a9_1

arm_a9 v19.1

Parameters address_map <address-map><slave name='bridges.axi_h2f' start='0xC0000000' end='0xE0000000' datawidth='32' /><slave name='bridges.axi_h2f_lw' start='0xFF200000' end='0xFF400000' datawidth='32' /><slave name='i_emac_emac0.axi_slave0' start='0xFF800000' end='0xFF802000' datawidth='32' /><slave name='i_emac_emac1.axi_slave0' start='0xFF802000' end='0xFF804000' datawidth='32' /><slave name='i_emac_emac2.axi_slave0' start='0xFF804000' end='0xFF806000' datawidth='32' /><slave name='i_sdmmc_sdmmc.axi_slave0' start='0xFF808000' end='0xFF809000' datawidth='32' /><slave name='i_qspi_QSPIDATA.axi_slave0' start='0xFF809000' end='0xFF809100' datawidth='32' /><slave name='i_qspi_QSPIDATA.axi_slave1' start='0xFFA00000' end='0xFFA00100' datawidth='32' /><slave name='i_usbotg_0_globgrp.axi_slave0' start='0xFFB00000' end='0xFFB40000' datawidth='32' /><slave name='i_usbotg_1_globgrp.axi_slave0' start='0xFFB40000' end='0xFFB80000' datawidth='32' /><slave name='i_nand_NANDDATA.axi_slave1' start='0xFFB80000' end='0xFFB90000' datawidth='32' /><slave name='i_nand_NANDDATA.axi_slave0' start='0xFFB90000' end='0xFFBA0000' datawidth='32' /><slave name='i_uart_0_uart.axi_slave0' start='0xFFC02000' end='0xFFC02100' datawidth='32' /><slave name='i_uart_1_uart.axi_slave0' start='0xFFC02100' end='0xFFC02200' datawidth='32' /><slave name='i_i2c_0_i2c.axi_slave0' start='0xFFC02200' end='0xFFC02300' datawidth='32' /><slave name='i_i2c_1_i2c.axi_slave0' start='0xFFC02300' end='0xFFC02400' datawidth='32' /><slave name='i_i2c_emac_0_i2c.axi_slave0' start='0xFFC02400' end='0xFFC02500' datawidth='32' /><slave name='i_i2c_emac_1_i2c.axi_slave0' start='0xFFC02500' end='0xFFC02600' datawidth='32' /><slave name='i_i2c_emac_2_i2c.axi_slave0' start='0xFFC02600' end='0xFFC02700' datawidth='32' /><slave name='i_timer_sp_0_timer.axi_slave0' start='0xFFC02700' end='0xFFC02800' datawidth='32' /><slave name='i_timer_sp_1_timer.axi_slave0' start='0xFFC02800' end='0xFFC02900' datawidth='32' /><slave name='i_gpio_0_gpio.axi_slave0' start='0xFFC02900' end='0xFFC02A00' datawidth='32' /><slave name='i_gpio_1_gpio.axi_slave0' start='0xFFC02A00' end='0xFFC02B00' datawidth='32' /><slave name='i_gpio_2_gpio.axi_slave0' start='0xFFC02B00' end='0xFFC02C00' datawidth='32' /><slave name='i_fpga_mgr_fpgamgrregs.axi_slave1' start='0xFFCFE400' end='0xFFCFE500' datawidth='32' /><slave name='i_timer_sys_0_timer.axi_slave0' start='0xFFD00000' end='0xFFD00100' datawidth='32' /><slave name='i_timer_sys_1_timer.axi_slave0' start='0xFFD00100' end='0xFFD00200' datawidth='32' /><slave name='i_watchdog_0_l4wd.axi_slave0' start='0xFFD00200' end='0xFFD00300' datawidth='32' /><slave name='i_watchdog_1_l4wd.axi_slave0' start='0xFFD00300' end='0xFFD00400' datawidth='32' /><slave name='i_fpga_mgr_fpgamgrregs.axi_slave0' start='0xFFD03000' end='0xFFD04000' datawidth='32' /><slave name='baum_clkmgr.axi_slave0' start='0xFFD04000' end='0xFFD05000' datawidth='32' /><slave name='i_rst_mgr_rstmgr.axi_slave0' start='0xFFD05000' end='0xFFD05100' datawidth='32' /><slave name='i_sys_mgr_core.axi_slave0' start='0xFFD06000' end='0xFFD06400' datawidth='32' /><slave name='i_dma_DMASECURE.axi_slave0' start='0xFFDA1000' end='0xFFDA2000' datawidth='32' /><slave name='i_spis_0_spis.axi_slave0' start='0xFFDA2000' end='0xFFDA2100' datawidth='32' /><slave name='i_spis_1_spis.axi_slave0' start='0xFFDA3000' end='0xFFDA3100' datawidth='32' /><slave name='i_spim_0_spim.axi_slave0' start='0xFFDA4000' end='0xFFDA4100' datawidth='32' /><slave name='i_spim_1_spim.axi_slave0' start='0xFFDA5000' end='0xFFDA5100' datawidth='32' /><slave name='scu.axi_slave0' start='0xFFFFC000' end='0xFFFFC100' datawidth='32' /><slave name='arm_gic_0.axi_slave1' start='0xFFFFC100' end='0xFFFFC200' datawidth='32' /><slave name='timer.axi_slave0' start='0xFFFFC600' end='0xFFFFC700' datawidth='32' /><slave name='arm_gic_0.axi_slave0' start='0xFFFFD000' end='0xFFFFE000' datawidth='32' /><slave name='mpu_reg_l2_MPUL2.axi_slave0' start='0xFFFFF000' end='0x100000000' datawidth='32' /></address-map> deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

a10_hps_arm_gic_0

arria10_arm_gic v19.1

Parameters deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

a10_hps_baum_clkmgr

baum_clkmgr v19.1

Parameters deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

a10_hps_mpu_reg_l2_MPUL2

arm_pl310_L2 v19.1

Parameters deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

a10_hps_i_dma_DMASECURE

arm_pl330_dma v19.1

Parameters deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

a10_hps_i_sys_mgr_core

altera_sysmgr v19.1

Parameters cpu1_start_addr 4291846704 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

a10_hps_i_rst_mgr_rstmgr

altera_rstmgr v19.1

Parameters offset 32 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

a10_hps_i_fpga_mgr_fpgamgrregs

altera_fpgamgr v19.1

Parameters compatible altr,socfpga-a10-fpga-mgr deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

a10_hps_timer

arm_internal_timer v19.1

Parameters deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

a10_hps_i_timer_sp_0_timer

dw_apb_timer_sp v19.1

Parameters deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

a10_hps_i_timer_sp_1_timer

dw_apb_timer_sp v19.1

Parameters deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

a10_hps_i_timer_sys_0_timer

dw_apb_timer_osc v19.1

Parameters deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

a10_hps_i_timer_sys_1_timer

dw_apb_timer_osc v19.1

Parameters deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

a10_hps_i_watchdog_0_l4wd

dw_wd_timer v19.1

Parameters deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

a10_hps_i_watchdog_1_l4wd

dw_wd_timer v19.1

Parameters deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

a10_hps_i_gpio_0_gpio

dw_gpio v19.1

Parameters embeddedsw.dts.instance.GPIO_PORTA_INTR 1 embeddedsw.dts.instance.GPIO_PWIDTH_A 24 embeddedsw.dts.instance.GPIO_PWIDTH_B 0 embeddedsw.dts.instance.GPIO_PWIDTH_C 0 embeddedsw.dts.instance.GPIO_PWIDTH_D 0 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

a10_hps_i_gpio_1_gpio

dw_gpio v19.1

Parameters embeddedsw.dts.instance.GPIO_PORTA_INTR 1 embeddedsw.dts.instance.GPIO_PWIDTH_A 24 embeddedsw.dts.instance.GPIO_PWIDTH_B 0 embeddedsw.dts.instance.GPIO_PWIDTH_C 0 embeddedsw.dts.instance.GPIO_PWIDTH_D 0 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

a10_hps_i_gpio_2_gpio

dw_gpio v19.1

Parameters embeddedsw.dts.instance.GPIO_PORTA_INTR 1 embeddedsw.dts.instance.GPIO_PWIDTH_A 14 embeddedsw.dts.instance.GPIO_PWIDTH_B 0 embeddedsw.dts.instance.GPIO_PWIDTH_C 0 embeddedsw.dts.instance.GPIO_PWIDTH_D 0 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

a10_hps_i_uart_0_uart

snps_uart v19.1

Parameters swEnabled false clk_freq_mhz 0.0 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments FIFO_DEPTH 128 FIFO_HWFC 0 FIFO_MODE 1 FIFO_SWFC 0 FREQ 0

---

a10_hps_i_uart_1_uart

snps_uart v19.1

Parameters swEnabled true clk_freq_mhz 0.0 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments FIFO_DEPTH 128 FIFO_HWFC 0 FIFO_MODE 1 FIFO_SWFC 0 FREQ 0

---

a10_hps_i_emac_emac0

stmmac v19.1

Parameters swEnabled true compatible altr,socfpga-stmmac snps,dwmac-3.72a snps,dwmac rx_fifo_depth 16384 tx_fifo_depth 4096 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

a10_hps_i_emac_emac1

stmmac v19.1

Parameters swEnabled false compatible altr,socfpga-stmmac snps,dwmac-3.72a snps,dwmac rx_fifo_depth 16384 tx_fifo_depth 4096 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

a10_hps_i_emac_emac2

stmmac v19.1

Parameters swEnabled false compatible altr,socfpga-stmmac snps,dwmac-3.72a snps,dwmac rx_fifo_depth 16384 tx_fifo_depth 4096 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

a10_hps_i_spim_0_spim

spi v19.1

Parameters swEnabled false deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

a10_hps_i_spim_1_spim

spi v19.1

Parameters swEnabled true deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

a10_hps_i_spis_0_spis

spi v19.1

Parameters swEnabled false deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

a10_hps_i_spis_1_spis

spi v19.1

Parameters swEnabled false deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

a10_hps_i_i2c_0_i2c

designware_i2c v19.1

Parameters swEnabled false deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

a10_hps_i_i2c_1_i2c

designware_i2c v19.1

Parameters swEnabled true deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

a10_hps_i_i2c_emac_0_i2c

designware_i2c v19.1

Parameters swEnabled false deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

a10_hps_i_i2c_emac_1_i2c

designware_i2c v19.1

Parameters swEnabled false deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

a10_hps_i_i2c_emac_2_i2c

designware_i2c v19.1

Parameters swEnabled false deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

a10_hps_i_qspi_QSPIDATA

cadence_qspi v19.1

Parameters swEnabled true deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

a10_hps_i_sdmmc_sdmmc

sdmmc v19.1

Parameters swEnabled false deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

a10_hps_i_nand_NANDDATA

denali_nand v19.1

Parameters swEnabled false deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

a10_hps_i_usbotg_0_globgrp

usb v19.1

Parameters swEnabled true deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

a10_hps_i_usbotg_1_globgrp

usb v19.1

Parameters swEnabled false deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

a10_hps_scu

scu v19.1

Parameters deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

button_pio

altera_avalon_pio v19.1

Parameters generateLegacySim false

  

Software Assignments BIT_CLEARING_EDGE_REGISTER 1 BIT_MODIFYING_OUTPUT_REGISTER 0 CAPTURE 1 DATA_WIDTH 4 DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0 EDGE_TYPE FALLING FREQ 100000000 HAS_IN 1 HAS_OUT 0 HAS_TRI 0 IRQ_TYPE EDGE RESET_VALUE 0

---

clk_100

altera_clock_bridge v19.1

Parameters generateLegacySim false

  

Software Assignments (none)

---

dipsw_pio

altera_avalon_pio v19.1

Parameters generateLegacySim false

  

Software Assignments BIT_CLEARING_EDGE_REGISTER 1 BIT_MODIFYING_OUTPUT_REGISTER 0 CAPTURE 1 DATA_WIDTH 4 DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0 EDGE_TYPE ANY FREQ 100000000 HAS_IN 1 HAS_OUT 0 HAS_TRI 0 IRQ_TYPE EDGE RESET_VALUE 0

---

emif_hps

altera_emif_a10_hps v19.1.0

Parameters generateLegacySim false

  

Software Assignments (none)

---

f2sdram0_m

altera_jtag_avalon_master v19.1

Parameters generateLegacySim false

  

Software Assignments (none)

---

f2sdram2_m

altera_jtag_avalon_master v19.1

Parameters generateLegacySim false

  

Software Assignments (none)

---

fpga_m

altera_jtag_avalon_master v19.1

Parameters generateLegacySim false

  

Software Assignments (none)

---

hps_m

altera_jtag_avalon_master v19.1

Parameters generateLegacySim false

  

Software Assignments (none)

---

issp_0

altera_in_system_sources_probes v19.1

Parameters generateLegacySim false

  

Software Assignments (none)

---

led_pio

altera_avalon_pio v19.1

Parameters generateLegacySim false

  

Software Assignments BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 CAPTURE 0 DATA_WIDTH 4 DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0 EDGE_TYPE NONE FREQ 100000000 HAS_IN 1 HAS_OUT 1 HAS_TRI 0 IRQ_TYPE NONE RESET_VALUE 0