MPU_EVENTS_Enable |
false |
GP_Enable |
false |
DEBUG_APB_Enable |
false |
STM_Enable |
true |
CTI_Enable |
false |
DDR_ATB_Enable |
false |
F2S_mode |
0 |
F2S_Width |
3 |
F2S_ready_latency |
0 |
F2S_ADDRESS_WIDTH |
32 |
S2F_Width |
3 |
S2F_ready_latency |
0 |
S2F_ADDRESS_WIDTH |
32 |
LWH2F_Enable |
1 |
LWH2F_ready_latency |
0 |
LWH2F_ADDRESS_WIDTH |
21 |
F2SDRAM0_Width |
3 |
F2SDRAM0_ready_latency |
0 |
F2SDRAM1_Width |
3 |
F2SDRAM1_ready_latency |
0 |
F2SDRAM2_Width |
3 |
F2SDRAM2_ready_latency |
0 |
F2SDRAM_ADDRESS_WIDTH |
32 |
HPS_BOOT |
1 |
DMA_PeriphId_DERIVED |
0,1,2,3,4,5,6,7 |
DMA_Enable |
No,No,No,No,No,No,No,No |
F2SINTERRUPT_Enable |
true |
S2FINTERRUPT_CLOCKPERIPHERAL_Enable |
false |
S2FINTERRUPT_DMA_Enable |
false |
S2FINTERRUPT_EMAC0_Enable |
false |
S2FINTERRUPT_EMAC1_Enable |
false |
S2FINTERRUPT_EMAC2_Enable |
false |
S2FINTERRUPT_GPIO_Enable |
false |
S2FINTERRUPT_I2CEMAC0_Enable |
false |
S2FINTERRUPT_I2CEMAC1_Enable |
false |
S2FINTERRUPT_I2CEMAC2_Enable |
false |
S2FINTERRUPT_I2C0_Enable |
false |
S2FINTERRUPT_I2C1_Enable |
false |
S2FINTERRUPT_L4TIMER_Enable |
false |
S2FINTERRUPT_NAND_Enable |
false |
S2FINTERRUPT_SYSTIMER_Enable |
false |
S2FINTERRUPT_SDMMC_Enable |
false |
S2FINTERRUPT_SPIM0_Enable |
false |
S2FINTERRUPT_SPIM1_Enable |
false |
S2FINTERRUPT_SPIS0_Enable |
false |
S2FINTERRUPT_SPIS1_Enable |
false |
S2FINTERRUPT_SYSTEMMANAGER_Enable |
false |
S2FINTERRUPT_UART0_Enable |
false |
S2FINTERRUPT_UART1_Enable |
false |
S2FINTERRUPT_USB0_Enable |
false |
S2FINTERRUPT_USB1_Enable |
false |
S2FINTERRUPT_WATCHDOG_Enable |
false |
eosc1_clk_mhz |
25.0 |
F2H_FREE_CLK_Enable |
false |
F2H_FREE_CLK_FREQ |
200 |
FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_MD_CLK |
2.5 |
FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_GTX_CLK |
100 |
FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_MD_CLK |
2.5 |
FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_GTX_CLK |
125 |
FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC2_MD_CLK |
2.5 |
FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC2_GTX_CLK |
125 |
FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SDMMC_CCLK |
100 |
FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM0_SCLK_OUT |
100 |
FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM1_SCLK_OUT |
100 |
FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C0_CLK |
100 |
FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C1_CLK |
100 |
FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2CEMAC0_CLK |
100 |
FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2CEMAC1_CLK |
100 |
FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2CEMAC2_CLK |
100 |
DEFAULT_MPU_CLK |
1000 |
MPU_CLK_VCCL |
1 |
USE_DEFAULT_MPU_CLK |
false |
CUSTOM_MPU_CLK |
800 |
H2F_USER0_CLK_Enable |
false |
H2F_USER0_CLK_FREQ |
500 |
H2F_USER1_CLK_Enable |
false |
H2F_USER1_CLK_FREQ |
500 |
L3_MAIN_FREE_CLK |
400 |
L4_SYS_FREE_CLK |
1 |
NOCDIV_L4MAINCLK |
0 |
NOCDIV_L4MPCLK |
1 |
NOCDIV_L4SPCLK |
2 |
NOCDIV_CS_ATCLK |
0 |
NOCDIV_CS_PDBGCLK |
1 |
NOCDIV_CS_TRACECLK |
0 |
HPS_DIV_GPIO_FREQ2 |
200 |
EMAC0_CLK |
250 |
EMAC1_CLK |
250 |
EMAC2_CLK |
250 |
CLK_MAIN_PLL_SOURCE2 |
0 |
CLK_PERI_PLL_SOURCE2 |
0 |
CLK_S2F_USER0_SOURCE |
1 |
CLK_S2F_USER1_SOURCE |
1 |
CLK_PSI_SOURCE |
1 |
CLK_EMAC_PTP_SOURCE |
1 |
CLK_GPIO_SOURCE |
0 |
CLK_SDMMC_SOURCE |
0 |
CLK_EMACA_SOURCE |
1 |
CLK_EMACB_SOURCE |
1 |
H2F_PENDING_RST_Enable |
false |
H2F_COLD_RST_Enable |
false |
watchdog_reset |
true |
W_RESET_ACTION |
0 |
EMIF_CONDUIT_Enable |
true |
IO_INPUT_DELAY0 |
0 |
IO_OUTPUT_DELAY0 |
0 |
IO_INPUT_DELAY1 |
0 |
IO_OUTPUT_DELAY1 |
0 |
IO_INPUT_DELAY2 |
0 |
IO_OUTPUT_DELAY2 |
0 |
IO_INPUT_DELAY3 |
0 |
IO_OUTPUT_DELAY3 |
0 |
IO_INPUT_DELAY4 |
0 |
IO_OUTPUT_DELAY4 |
0 |
IO_INPUT_DELAY5 |
0 |
IO_OUTPUT_DELAY5 |
0 |
IO_INPUT_DELAY6 |
0 |
IO_OUTPUT_DELAY6 |
0 |
IO_INPUT_DELAY7 |
0 |
IO_OUTPUT_DELAY7 |
0 |
IO_INPUT_DELAY8 |
0 |
IO_OUTPUT_DELAY8 |
0 |
IO_INPUT_DELAY9 |
0 |
IO_OUTPUT_DELAY9 |
0 |
IO_INPUT_DELAY10 |
0 |
IO_OUTPUT_DELAY10 |
0 |
IO_INPUT_DELAY11 |
0 |
IO_OUTPUT_DELAY11 |
0 |
IO_INPUT_DELAY12 |
0 |
IO_OUTPUT_DELAY12 |
17 |
IO_INPUT_DELAY13 |
0 |
IO_OUTPUT_DELAY13 |
0 |
IO_INPUT_DELAY14 |
0 |
IO_OUTPUT_DELAY14 |
0 |
IO_INPUT_DELAY15 |
0 |
IO_OUTPUT_DELAY15 |
0 |
IO_INPUT_DELAY16 |
0 |
IO_OUTPUT_DELAY16 |
0 |
IO_INPUT_DELAY17 |
0 |
IO_OUTPUT_DELAY17 |
0 |
IO_INPUT_DELAY18 |
0 |
IO_OUTPUT_DELAY18 |
0 |
IO_INPUT_DELAY19 |
0 |
IO_OUTPUT_DELAY19 |
0 |
IO_INPUT_DELAY20 |
0 |
IO_OUTPUT_DELAY20 |
0 |
IO_INPUT_DELAY21 |
0 |
IO_OUTPUT_DELAY21 |
0 |
IO_INPUT_DELAY22 |
0 |
IO_OUTPUT_DELAY22 |
0 |
IO_INPUT_DELAY23 |
0 |
IO_OUTPUT_DELAY23 |
0 |
IO_INPUT_DELAY24 |
0 |
IO_OUTPUT_DELAY24 |
0 |
IO_INPUT_DELAY25 |
0 |
IO_OUTPUT_DELAY25 |
0 |
IO_INPUT_DELAY26 |
0 |
IO_OUTPUT_DELAY26 |
0 |
IO_INPUT_DELAY27 |
0 |
IO_OUTPUT_DELAY27 |
0 |
IO_INPUT_DELAY28 |
0 |
IO_OUTPUT_DELAY28 |
0 |
IO_INPUT_DELAY29 |
0 |
IO_OUTPUT_DELAY29 |
0 |
IO_INPUT_DELAY30 |
0 |
IO_OUTPUT_DELAY30 |
0 |
IO_INPUT_DELAY31 |
0 |
IO_OUTPUT_DELAY31 |
0 |
IO_INPUT_DELAY32 |
0 |
IO_OUTPUT_DELAY32 |
0 |
IO_INPUT_DELAY33 |
0 |
IO_OUTPUT_DELAY33 |
0 |
IO_INPUT_DELAY34 |
0 |
IO_OUTPUT_DELAY34 |
0 |
IO_INPUT_DELAY35 |
0 |
IO_OUTPUT_DELAY35 |
0 |
IO_INPUT_DELAY36 |
0 |
IO_OUTPUT_DELAY36 |
0 |
IO_INPUT_DELAY37 |
0 |
IO_OUTPUT_DELAY37 |
0 |
IO_INPUT_DELAY38 |
0 |
IO_OUTPUT_DELAY38 |
0 |
IO_INPUT_DELAY39 |
0 |
IO_OUTPUT_DELAY39 |
0 |
IO_INPUT_DELAY40 |
0 |
IO_OUTPUT_DELAY40 |
0 |
IO_INPUT_DELAY41 |
0 |
IO_OUTPUT_DELAY41 |
0 |
IO_INPUT_DELAY42 |
0 |
IO_OUTPUT_DELAY42 |
0 |
IO_INPUT_DELAY43 |
0 |
IO_OUTPUT_DELAY43 |
0 |
IO_INPUT_DELAY44 |
0 |
IO_OUTPUT_DELAY44 |
0 |
IO_INPUT_DELAY45 |
0 |
IO_OUTPUT_DELAY45 |
0 |
IO_INPUT_DELAY46 |
0 |
IO_OUTPUT_DELAY46 |
0 |
IO_INPUT_DELAY47 |
0 |
IO_OUTPUT_DELAY47 |
0 |
EMAC0_PTP |
false |
EMAC1_PTP |
false |
EMAC2_PTP |
false |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |