subsys_jtg_mst |
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2018.12.27.15:21:32 | Datasheet |
f2sdram_m_0 | f2sdram_m_1 | f2sdram_m_2 | fpga_m | hps_m | |
master | master | master | master | master |
jtag_clk | out_clk | f2sdram_m_0 |
clk | ||
jtag_rst_in | out_reset | |
clk_reset |
Parameters
|
Software Assignments(none) |
jtag_clk | out_clk | f2sdram_m_1 |
clk | ||
jtag_rst_in | out_reset | |
clk_reset |
Parameters
|
Software Assignments(none) |
jtag_clk | out_clk | f2sdram_m_2 |
clk | ||
jtag_rst_in | out_reset | |
clk_reset |
Parameters
|
Software Assignments(none) |
jtag_clk | out_clk | fpga_m |
clk | ||
jtag_rst_in | out_reset | |
clk_reset |
Parameters
|
Software Assignments(none) |
jtag_clk | out_clk | hps_m |
clk | ||
jtag_rst_in | out_reset | |
clk_reset |
Parameters
|
Software Assignments(none) |
Parameters
|
Software Assignments(none) |
jtag_clk | out_clk | jtag_rst_in | |
clk | |||
out_reset | fpga_m | ||
clk_reset | |||
out_reset | hps_m | ||
clk_reset | |||
out_reset | f2sdram_m_0 | ||
clk_reset | |||
out_reset | f2sdram_m_1 | ||
clk_reset | |||
out_reset | f2sdram_m_2 | ||
clk_reset |
Parameters
|
Software Assignments(none) |
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