qsys_top |
|
2018.12.27.15:19:09 | Datasheet |
hps_mge_mge_rcfg_0 | jtg_mst | jtg_mst_f2sdram_m_0 | jtg_mst_f2sdram_m_1 | jtg_mst_f2sdram_m_2 | jtg_mst_fpga_m | jtg_mst_hps_m | |||||
reconfig_xcvr_master | f2sdram_m_0_master | f2sdram_m_1_master | f2sdram_m_2_master | fpga_m_master | hps_m_master | master | master | master | master | master | |
mge_led_pio | |||||||||||
s1 | 0x00000100 | 0x00000100 | |||||||||
mge_rcfg_pio | |||||||||||
s1 | 0x00000110 | 0x00000110 | |||||||||
ocm | |||||||||||
s1 | 0x00040000 | 0x00040000 | |||||||||
sysid | |||||||||||
control_slave | 0x00000000 | 0x00000000 | |||||||||
hps_mge | |||||||||||
pb_s | |||||||||||
hps_mge_alt_mge_phy_1 | |||||||||||
avalon_mm_csr | 0x00010000 | 0x00010000 | |||||||||
reconfig_avmm | 0x00000000 | ||||||||||
hps_mge_alt_mge_phy_2 | |||||||||||
avalon_mm_csr | 0x00010080 | 0x00010080 | |||||||||
reconfig_avmm | 0x00002000 | ||||||||||
hps_mge_hps_to_mge_gmii_adapter_1 | |||||||||||
csr | 0x00010040 | 0x00010040 | |||||||||
hps_mge_hps_to_mge_gmii_adapter_2 | |||||||||||
csr | 0x000100c0 | 0x000100c0 | |||||||||
periph | |||||||||||
pb_cpu_0_s0 | |||||||||||
periph_ILC | |||||||||||
avalon_slave | 0x00001100 | 0x00001100 | |||||||||
periph_button_pio | |||||||||||
s1 | 0x00001060 | 0x00001060 | |||||||||
periph_dipsw_pio | |||||||||||
s1 | 0x00001070 | 0x00001070 | |||||||||
periph_led_pio | |||||||||||
s1 | 0x00001080 | 0x00001080 |
Parameters
|
Software Assignments(none) |
Parameters
|
Software Assignments(none) |
Parameters
|
Software Assignments(none) |
jtg_mst_fpga_m | master | fpga_m2ocm_pb | |
s0 | |||
clk_100 | out_clk | ||
clk | |||
rst_in | out_reset | ||
reset | |||
m0 | ocm | ||
s1 |
Parameters
|
Software Assignments(none) |
jtg_mst_fpga_m | master | mge_led_pio |
s1 | ||
s10_hps | h2f_lw_axi_master | |
s1 | ||
enet_refclk | out_clk | |
clk | ||
rst_in | out_reset | |
reset |
Parameters
|
Software Assignments
|
jtg_mst_fpga_m | master | mge_rcfg_pio |
s1 | ||
s10_hps | h2f_lw_axi_master | |
s1 | ||
enet_refclk | out_clk | |
clk | ||
rst_in | out_reset | |
reset |
Parameters
|
Software Assignments
|
s10_hps | h2f_axi_master | ocm |
s1 | ||
fpga_m2ocm_pb | m0 | |
s1 | ||
clk_100 | out_clk | |
clk1 | ||
rst_in | out_reset | |
reset1 |
Parameters
|
Software Assignments
|
clk_100 | out_clk | rst_in | |
clk | |||
out_reset | s10_hps | ||
f2h_axi_reset | |||
out_reset | |||
f2sdram0_reset | |||
out_reset | |||
f2sdram1_reset | |||
out_reset | |||
f2sdram2_reset | |||
out_reset | |||
h2f_axi_reset | |||
out_reset | |||
h2f_lw_axi_reset | |||
out_reset | sysid | ||
reset | |||
out_reset | jtg_mst_jtag_rst_in | ||
in_reset | |||
out_reset | fpga_m2ocm_pb | ||
reset | |||
out_reset | periph_periph_rst_in | ||
in_reset | |||
out_reset | mge_led_pio | ||
reset | |||
out_reset | mge_rcfg_pio | ||
reset | |||
out_reset | ocm | ||
reset1 | |||
out_reset | hps_mge_mge_rst_125M | ||
in_reset |
Parameters
|
Software Assignments(none) |
jtg_mst_f2sdram_m_0 | master | s10_hps | |
f2sdram0_data | |||
jtg_mst_f2sdram_m_1 | master | ||
f2sdram1_data | |||
jtg_mst_f2sdram_m_2 | master | ||
f2sdram2_data | |||
jtg_mst_hps_m | master | ||
f2h_axi_slave | |||
hps_mge_emac_splitter_1 | emac_rx_clk_in | ||
emac1_rx_clk_in | |||
emac_tx_clk_in | |||
emac1_tx_clk_in | |||
emac | |||
emac1 | |||
hps_mge_emac_splitter_2 | emac_rx_clk_in | ||
emac2_rx_clk_in | |||
emac_tx_clk_in | |||
emac2_tx_clk_in | |||
emac | |||
emac2 | |||
clk_100 | out_clk | ||
emac_ptp_ref_clock | |||
out_clk | |||
f2h_axi_clock | |||
out_clk | |||
f2sdram0_clock | |||
out_clk | |||
f2sdram1_clock | |||
out_clk | |||
f2sdram2_clock | |||
out_clk | |||
h2f_axi_clock | |||
enet_refclk | out_clk | ||
h2f_lw_axi_clock | |||
emif_hps | hps_emif | ||
hps_emif | |||
rst_in | out_reset | ||
f2h_axi_reset | |||
out_reset | |||
f2sdram0_reset | |||
out_reset | |||
f2sdram1_reset | |||
out_reset | |||
f2sdram2_reset | |||
out_reset | |||
h2f_axi_reset | |||
out_reset | |||
h2f_lw_axi_reset | |||
h2f_axi_master | ocm | ||
s1 | |||
h2f_lw_axi_master | sysid | ||
control_slave | |||
h2f_lw_axi_master | periph_pb_cpu_0 | ||
s0 | |||
h2f_lw_axi_master | hps_mge_pb_0 | ||
s0 | |||
h2f_lw_axi_master | mge_led_pio | ||
s1 | |||
h2f_lw_axi_master | mge_rcfg_pio | ||
s1 | |||
emac1_gtx_clk | hps_mge_emac_splitter_1 | ||
emac_gtx_clk | |||
emac1_rx_reset | |||
emac_rx_reset | |||
emac1_tx_reset | |||
emac_tx_reset | |||
emac2_gtx_clk | hps_mge_emac_splitter_2 | ||
emac_gtx_clk | |||
emac2_rx_reset | |||
emac_rx_reset | |||
emac2_tx_reset | |||
emac_tx_reset | |||
f2h_irq0 | periph_button_pio | ||
irq | |||
f2h_irq0 | periph_dipsw_pio | ||
irq |
Parameters
|
Software Assignments(none) |
clk_100 | out_clk | src_prb_rst |
source_clk |
Parameters
|
Software Assignments(none) |
jtg_mst_fpga_m | master | sysid |
control_slave | ||
s10_hps | h2f_lw_axi_master | |
control_slave | ||
clk_100 | out_clk | |
clk | ||
rst_in | out_reset | |
reset |
Parameters
|
Software Assignments
|
Parameters
|
Software Assignments(none) |
hps_mge_pb_0 | m0 | hps_mge_alt_mge_phy_1 | |
avalon_mm_csr | |||
hps_mge_pb_mge_rcfg_0 | m0 | ||
reconfig_avmm | |||
hps_mge_mge_enet_refclk | out_clk | ||
csr_clk | |||
out_clk | |||
reconfig_clk | |||
out_clk | |||
rx_cdr_refclk_0 | |||
hps_mge_hps_to_mge_gmii_adapter_1 | gmii16b_tx_d | ||
gmii16b_tx_d | |||
gmii16b_tx_en | |||
gmii16b_tx_en | |||
gmii16b_tx_err | |||
gmii16b_tx_err | |||
hps_mge_xcvr_reset_1 | rx_analogreset | ||
rx_analogreset | |||
rx_analogreset_stat | |||
rx_analogreset_stat | |||
rx_digitalreset | |||
rx_digitalreset | |||
rx_digitalreset_stat | |||
rx_digitalreset_stat | |||
rx_is_lockedtodata | |||
rx_is_lockedtodata | |||
tx_analogreset | |||
tx_analogreset | |||
tx_analogreset_stat | |||
tx_analogreset_stat | |||
tx_digitalreset | |||
tx_digitalreset | |||
tx_digitalreset_stat | |||
tx_digitalreset_stat | |||
hps_mge_mge_rcfg_0 | xcvr_mode_chan1 | ||
xcvr_mode | |||
hps_mge_mge_rst_125M | out_reset | ||
reconfig_reset | |||
out_reset | |||
reset | |||
rx_clkout | hps_mge_hps_to_mge_gmii_adapter_1 | ||
phy_rx_clkout | |||
tx_clkout | |||
phy_tx_clkout | |||
gmii16b_rx_d | |||
gmii16b_rx_d | |||
gmii16b_rx_dv | |||
gmii16b_rx_dv | |||
gmii16b_rx_err | |||
gmii16b_rx_err | |||
operating_speed | |||
phy_speed | |||
rx_clkena | |||
phy_rx_clkena | |||
tx_clkena | |||
phy_tx_clkena | |||
rx_cal_busy | hps_mge_mge_rcfg_0 | ||
rx_cal_busy_chan1 | |||
tx_cal_busy | |||
tx_cal_busy_chan1 |
Parameters
|
Software Assignments(none) |
hps_mge_pb_0 | m0 | hps_mge_alt_mge_phy_2 | |
avalon_mm_csr | |||
hps_mge_pb_mge_rcfg_0 | m0 | ||
reconfig_avmm | |||
hps_mge_mge_enet_refclk | out_clk | ||
csr_clk | |||
out_clk | |||
reconfig_clk | |||
out_clk | |||
rx_cdr_refclk_0 | |||
hps_mge_hps_to_mge_gmii_adapter_2 | gmii16b_tx_d | ||
gmii16b_tx_d | |||
gmii16b_tx_en | |||
gmii16b_tx_en | |||
gmii16b_tx_err | |||
gmii16b_tx_err | |||
hps_mge_xcvr_reset_2 | rx_analogreset | ||
rx_analogreset | |||
rx_analogreset_stat | |||
rx_analogreset_stat | |||
rx_digitalreset | |||
rx_digitalreset | |||
rx_digitalreset_stat | |||
rx_digitalreset_stat | |||
rx_is_lockedtodata | |||
rx_is_lockedtodata | |||
tx_analogreset | |||
tx_analogreset | |||
tx_analogreset_stat | |||
tx_analogreset_stat | |||
tx_digitalreset | |||
tx_digitalreset | |||
tx_digitalreset_stat | |||
tx_digitalreset_stat | |||
hps_mge_mge_rcfg_0 | xcvr_mode_chan2 | ||
xcvr_mode | |||
hps_mge_mge_rst_125M | out_reset | ||
reconfig_reset | |||
out_reset | |||
reset | |||
rx_clkout | hps_mge_hps_to_mge_gmii_adapter_2 | ||
phy_rx_clkout | |||
tx_clkout | |||
phy_tx_clkout | |||
gmii16b_rx_d | |||
gmii16b_rx_d | |||
gmii16b_rx_dv | |||
gmii16b_rx_dv | |||
gmii16b_rx_err | |||
gmii16b_rx_err | |||
operating_speed | |||
phy_speed | |||
rx_clkena | |||
phy_rx_clkena | |||
tx_clkena | |||
phy_tx_clkena | |||
rx_cal_busy | hps_mge_mge_rcfg_0 | ||
rx_cal_busy_chan2 | |||
tx_cal_busy | |||
tx_cal_busy_chan2 |
Parameters
|
Software Assignments(none) |
s10_hps | emac1_gtx_clk | hps_mge_emac_splitter_1 | |
emac_gtx_clk | |||
emac1_rx_reset | |||
emac_rx_reset | |||
emac1_tx_reset | |||
emac_tx_reset | |||
hps_gmii | hps_mge_hps_to_mge_gmii_adapter_1 | ||
hps_gmii | |||
emac_rx_clk_in | s10_hps | ||
emac1_rx_clk_in | |||
emac_tx_clk_in | |||
emac1_tx_clk_in | |||
emac | |||
emac1 |
Parameters
|
Software Assignments(none) |
s10_hps | emac2_gtx_clk | hps_mge_emac_splitter_2 | |
emac_gtx_clk | |||
emac2_rx_reset | |||
emac_rx_reset | |||
emac2_tx_reset | |||
emac_tx_reset | |||
hps_gmii | hps_mge_hps_to_mge_gmii_adapter_2 | ||
hps_gmii | |||
emac_rx_clk_in | s10_hps | ||
emac2_rx_clk_in | |||
emac_tx_clk_in | |||
emac2_tx_clk_in | |||
emac | |||
emac2 |
Parameters
|
Software Assignments(none) |
hps_mge_mge_enet_refclk | out_clk | hps_mge_enet_iopll_0 | |
refclk | |||
hps_mge_mge_rst_125M | out_reset | ||
reset | |||
outclk0 | hps_mge_hps_to_mge_gmii_adapter_1 | ||
pll_125m_clk | |||
outclk1 | |||
pll_25m_clk | |||
outclk2 | |||
pll_2_5m_clk | |||
outclk0 | hps_mge_hps_to_mge_gmii_adapter_2 | ||
pll_125m_clk | |||
outclk1 | |||
pll_25m_clk | |||
outclk2 | |||
pll_2_5m_clk |
Parameters
|
Software Assignments(none) |
hps_mge_pb_0 | m0 | hps_mge_hps_to_mge_gmii_adapter_1 | |
csr | |||
hps_mge_mge_enet_refclk | out_clk | ||
clock | |||
hps_mge_enet_iopll_0 | outclk0 | ||
pll_125m_clk | |||
outclk1 | |||
pll_25m_clk | |||
outclk2 | |||
pll_2_5m_clk | |||
hps_mge_alt_mge_phy_1 | rx_clkout | ||
phy_rx_clkout | |||
tx_clkout | |||
phy_tx_clkout | |||
gmii16b_rx_d | |||
gmii16b_rx_d | |||
gmii16b_rx_dv | |||
gmii16b_rx_dv | |||
gmii16b_rx_err | |||
gmii16b_rx_err | |||
operating_speed | |||
phy_speed | |||
rx_clkena | |||
phy_rx_clkena | |||
tx_clkena | |||
phy_tx_clkena | |||
hps_mge_emac_splitter_1 | hps_gmii | ||
hps_gmii | |||
hps_mge_mge_rst_125M | out_reset | ||
reset_sink | |||
gmii16b_tx_d | hps_mge_alt_mge_phy_1 | ||
gmii16b_tx_d | |||
gmii16b_tx_en | |||
gmii16b_tx_en | |||
gmii16b_tx_err | |||
gmii16b_tx_err |
Parameters
|
Software Assignments(none) |
hps_mge_pb_0 | m0 | hps_mge_hps_to_mge_gmii_adapter_2 | |
csr | |||
hps_mge_mge_enet_refclk | out_clk | ||
clock | |||
hps_mge_enet_iopll_0 | outclk0 | ||
pll_125m_clk | |||
outclk1 | |||
pll_25m_clk | |||
outclk2 | |||
pll_2_5m_clk | |||
hps_mge_alt_mge_phy_2 | rx_clkout | ||
phy_rx_clkout | |||
tx_clkout | |||
phy_tx_clkout | |||
gmii16b_rx_d | |||
gmii16b_rx_d | |||
gmii16b_rx_dv | |||
gmii16b_rx_dv | |||
gmii16b_rx_err | |||
gmii16b_rx_err | |||
operating_speed | |||
phy_speed | |||
rx_clkena | |||
phy_rx_clkena | |||
tx_clkena | |||
phy_tx_clkena | |||
hps_mge_emac_splitter_2 | hps_gmii | ||
hps_gmii | |||
hps_mge_mge_rst_125M | out_reset | ||
reset_sink | |||
gmii16b_tx_d | hps_mge_alt_mge_phy_2 | ||
gmii16b_tx_d | |||
gmii16b_tx_en | |||
gmii16b_tx_en | |||
gmii16b_tx_err | |||
gmii16b_tx_err |
Parameters
|
Software Assignments(none) |
enet_refclk | out_clk | hps_mge_mge_enet_refclk | |
in_clk | |||
out_clk | hps_mge_mge_rst_125M | ||
clk | |||
out_clk | hps_mge_mge_rcfg_rst | ||
clk | |||
out_clk | hps_mge_pb_0 | ||
clk | |||
out_clk | hps_mge_pb_mge_rcfg_0 | ||
clk | |||
out_clk | hps_mge_mge_rcfg_0 | ||
clock | |||
out_clk | hps_mge_hps_to_mge_gmii_adapter_1 | ||
clock | |||
out_clk | hps_mge_xcvr_reset_1 | ||
clock | |||
out_clk | hps_mge_hps_to_mge_gmii_adapter_2 | ||
clock | |||
out_clk | hps_mge_xcvr_reset_2 | ||
clock | |||
out_clk | hps_mge_alt_mge_phy_1 | ||
csr_clk | |||
out_clk | |||
reconfig_clk | |||
out_clk | |||
rx_cdr_refclk_0 | |||
out_clk | hps_mge_alt_mge_phy_2 | ||
csr_clk | |||
out_clk | |||
reconfig_clk | |||
out_clk | |||
rx_cdr_refclk_0 | |||
out_clk | hps_mge_xcvr_fpll_1G | ||
pll_refclk0 | |||
out_clk | hps_mge_enet_iopll_0 | ||
refclk |
Parameters
|
Software Assignments(none) |
hps_mge_mge_enet_refclk | out_clk | hps_mge_mge_rcfg_0 | |
clock | |||
hps_mge_alt_mge_phy_1 | rx_cal_busy | ||
rx_cal_busy_chan1 | |||
tx_cal_busy | |||
tx_cal_busy_chan1 | |||
hps_mge_alt_mge_phy_2 | rx_cal_busy | ||
rx_cal_busy_chan2 | |||
tx_cal_busy | |||
tx_cal_busy_chan2 | |||
hps_mge_mge_rcfg_rst | out_reset | ||
reset_sink | |||
reconfig_xcvr_master | hps_mge_pb_mge_rcfg_0 | ||
s0 | |||
pll_select_chan1 | hps_mge_xcvr_reset_1 | ||
pll_select | |||
rx_cal_busy_chan1_out | |||
rx_cal_busy | |||
tx_cal_busy_chan1_out | |||
tx_cal_busy | |||
mge_chan1_resetn | |||
reset | |||
pll_select_chan2 | hps_mge_xcvr_reset_2 | ||
pll_select | |||
rx_cal_busy_chan2_out | |||
rx_cal_busy | |||
tx_cal_busy_chan2_out | |||
tx_cal_busy | |||
mge_chan2_resetn | |||
reset | |||
xcvr_mode_chan1 | hps_mge_alt_mge_phy_1 | ||
xcvr_mode | |||
xcvr_mode_chan2 | hps_mge_alt_mge_phy_2 | ||
xcvr_mode |
Parameters
|
Software Assignments(none) |
hps_mge_mge_enet_refclk | out_clk | hps_mge_mge_rcfg_rst | |
clk | |||
out_reset | hps_mge_mge_rcfg_0 | ||
reset_sink |
Parameters
|
Software Assignments(none) |
hps_mge_mge_enet_refclk | out_clk | hps_mge_mge_rst_125M | |
clk | |||
rst_in | out_reset | ||
in_reset | |||
out_reset | hps_mge_alt_mge_phy_1 | ||
reconfig_reset | |||
out_reset | |||
reset | |||
out_reset | hps_mge_alt_mge_phy_2 | ||
reconfig_reset | |||
out_reset | |||
reset | |||
out_reset | hps_mge_pb_0 | ||
reset | |||
out_reset | hps_mge_pb_mge_rcfg_0 | ||
reset | |||
out_reset | hps_mge_enet_iopll_0 | ||
reset | |||
out_reset | hps_mge_xcvr_reset_1 | ||
reset | |||
out_reset | hps_mge_xcvr_reset_2 | ||
reset | |||
out_reset | hps_mge_hps_to_mge_gmii_adapter_1 | ||
reset_sink | |||
out_reset | hps_mge_hps_to_mge_gmii_adapter_2 | ||
reset_sink |
Parameters
|
Software Assignments(none) |
hps_mge_mge_enet_refclk | out_clk | hps_mge_pb_0 | |
clk | |||
hps_mge_mge_rst_125M | out_reset | ||
reset | |||
jtg_mst_fpga_m | master | ||
s0 | |||
s10_hps | h2f_lw_axi_master | ||
s0 | |||
m0 | hps_mge_alt_mge_phy_1 | ||
avalon_mm_csr | |||
m0 | hps_mge_alt_mge_phy_2 | ||
avalon_mm_csr | |||
m0 | hps_mge_hps_to_mge_gmii_adapter_1 | ||
csr | |||
m0 | hps_mge_hps_to_mge_gmii_adapter_2 | ||
csr |
Parameters
|
Software Assignments(none) |
hps_mge_mge_rcfg_0 | reconfig_xcvr_master | hps_mge_pb_mge_rcfg_0 | |
s0 | |||
hps_mge_mge_enet_refclk | out_clk | ||
clk | |||
hps_mge_mge_rst_125M | out_reset | ||
reset | |||
m0 | hps_mge_alt_mge_phy_1 | ||
reconfig_avmm | |||
m0 | hps_mge_alt_mge_phy_2 | ||
reconfig_avmm |
Parameters
|
Software Assignments(none) |
hps_mge_mge_enet_refclk | out_clk | hps_mge_xcvr_fpll_1G |
pll_refclk0 |
Parameters
|
Software Assignments(none) |
hps_mge_mge_enet_refclk | out_clk | hps_mge_xcvr_reset_1 | |
clock | |||
hps_mge_mge_rcfg_0 | pll_select_chan1 | ||
pll_select | |||
rx_cal_busy_chan1_out | |||
rx_cal_busy | |||
tx_cal_busy_chan1_out | |||
tx_cal_busy | |||
mge_chan1_resetn | |||
reset | |||
hps_mge_mge_rst_125M | out_reset | ||
reset | |||
rx_analogreset | hps_mge_alt_mge_phy_1 | ||
rx_analogreset | |||
rx_analogreset_stat | |||
rx_analogreset_stat | |||
rx_digitalreset | |||
rx_digitalreset | |||
rx_digitalreset_stat | |||
rx_digitalreset_stat | |||
rx_is_lockedtodata | |||
rx_is_lockedtodata | |||
tx_analogreset | |||
tx_analogreset | |||
tx_analogreset_stat | |||
tx_analogreset_stat | |||
tx_digitalreset | |||
tx_digitalreset | |||
tx_digitalreset_stat | |||
tx_digitalreset_stat |
Parameters
|
Software Assignments(none) |
hps_mge_mge_enet_refclk | out_clk | hps_mge_xcvr_reset_2 | |
clock | |||
hps_mge_mge_rcfg_0 | pll_select_chan2 | ||
pll_select | |||
rx_cal_busy_chan2_out | |||
rx_cal_busy | |||
tx_cal_busy_chan2_out | |||
tx_cal_busy | |||
mge_chan2_resetn | |||
reset | |||
hps_mge_mge_rst_125M | out_reset | ||
reset | |||
rx_analogreset | hps_mge_alt_mge_phy_2 | ||
rx_analogreset | |||
rx_analogreset_stat | |||
rx_analogreset_stat | |||
rx_digitalreset | |||
rx_digitalreset | |||
rx_digitalreset_stat | |||
rx_digitalreset_stat | |||
rx_is_lockedtodata | |||
rx_is_lockedtodata | |||
tx_analogreset | |||
tx_analogreset | |||
tx_analogreset_stat | |||
tx_analogreset_stat | |||
tx_digitalreset | |||
tx_digitalreset | |||
tx_digitalreset_stat | |||
tx_digitalreset_stat |
Parameters
|
Software Assignments(none) |
Parameters
|
Software Assignments(none) |
jtg_mst_jtag_clk | out_clk | jtg_mst_f2sdram_m_0 | |
clk | |||
jtg_mst_jtag_rst_in | out_reset | ||
clk_reset | |||
master | s10_hps | ||
f2sdram0_data |
Parameters
|
Software Assignments(none) |
jtg_mst_jtag_clk | out_clk | jtg_mst_f2sdram_m_1 | |
clk | |||
jtg_mst_jtag_rst_in | out_reset | ||
clk_reset | |||
master | s10_hps | ||
f2sdram1_data |
Parameters
|
Software Assignments(none) |
jtg_mst_jtag_clk | out_clk | jtg_mst_f2sdram_m_2 | |
clk | |||
jtg_mst_jtag_rst_in | out_reset | ||
clk_reset | |||
master | s10_hps | ||
f2sdram2_data |
Parameters
|
Software Assignments(none) |
jtg_mst_jtag_clk | out_clk | jtg_mst_fpga_m | |
clk | |||
jtg_mst_jtag_rst_in | out_reset | ||
clk_reset | |||
master | sysid | ||
control_slave | |||
master | periph_pb_cpu_0 | ||
s0 | |||
master | hps_mge_pb_0 | ||
s0 | |||
master | fpga_m2ocm_pb | ||
s0 | |||
master | mge_led_pio | ||
s1 | |||
master | mge_rcfg_pio | ||
s1 |
Parameters
|
Software Assignments(none) |
jtg_mst_jtag_clk | out_clk | jtg_mst_hps_m | |
clk | |||
jtg_mst_jtag_rst_in | out_reset | ||
clk_reset | |||
master | s10_hps | ||
f2h_axi_slave |
Parameters
|
Software Assignments(none) |
clk_100 | out_clk | jtg_mst_jtag_clk | |
in_clk | |||
out_clk | jtg_mst_fpga_m | ||
clk | |||
out_clk | jtg_mst_jtag_rst_in | ||
clk | |||
out_clk | jtg_mst_hps_m | ||
clk | |||
out_clk | jtg_mst_f2sdram_m_0 | ||
clk | |||
out_clk | jtg_mst_f2sdram_m_1 | ||
clk | |||
out_clk | jtg_mst_f2sdram_m_2 | ||
clk |
Parameters
|
Software Assignments(none) |
jtg_mst_jtag_clk | out_clk | jtg_mst_jtag_rst_in | |
clk | |||
rst_in | out_reset | ||
in_reset | |||
out_reset | jtg_mst_fpga_m | ||
clk_reset | |||
out_reset | jtg_mst_hps_m | ||
clk_reset | |||
out_reset | jtg_mst_f2sdram_m_0 | ||
clk_reset | |||
out_reset | jtg_mst_f2sdram_m_1 | ||
clk_reset | |||
out_reset | jtg_mst_f2sdram_m_2 | ||
clk_reset |
Parameters
|
Software Assignments(none) |
Parameters
|
Software Assignments(none) |
periph_pb_cpu_0 | m0 | periph_ILC | |
avalon_slave | |||
periph_periph_clk | out_clk | ||
clk | |||
periph_periph_rst_in | out_reset | ||
reset_n | |||
irq | periph_button_pio | ||
irq | |||
irq | periph_dipsw_pio | ||
irq |
Parameters
|
Software Assignments(none) |
periph_pb_cpu_0 | m0 | periph_button_pio |
s1 | ||
periph_periph_clk | out_clk | |
clk | ||
periph_periph_rst_in | out_reset | |
reset | ||
periph_ILC | irq | |
irq | ||
s10_hps | f2h_irq0 | |
irq |
Parameters
|
Software Assignments
|
periph_pb_cpu_0 | m0 | periph_dipsw_pio |
s1 | ||
periph_periph_clk | out_clk | |
clk | ||
periph_periph_rst_in | out_reset | |
reset | ||
periph_ILC | irq | |
irq | ||
s10_hps | f2h_irq0 | |
irq |
Parameters
|
Software Assignments
|
periph_pb_cpu_0 | m0 | periph_led_pio |
s1 | ||
periph_periph_clk | out_clk | |
clk | ||
periph_periph_rst_in | out_reset | |
reset |
Parameters
|
Software Assignments
|
periph_periph_clk | out_clk | periph_pb_cpu_0 | |
clk | |||
periph_periph_rst_in | out_reset | ||
reset | |||
jtg_mst_fpga_m | master | ||
s0 | |||
s10_hps | h2f_lw_axi_master | ||
s0 | |||
m0 | periph_ILC | ||
avalon_slave | |||
m0 | periph_led_pio | ||
s1 | |||
m0 | periph_dipsw_pio | ||
s1 | |||
m0 | periph_button_pio | ||
s1 |
Parameters
|
Software Assignments(none) |
clk_100 | out_clk | periph_periph_clk | |
in_clk | |||
out_clk | periph_pb_cpu_0 | ||
clk | |||
out_clk | periph_periph_rst_in | ||
clk | |||
out_clk | periph_ILC | ||
clk | |||
out_clk | periph_led_pio | ||
clk | |||
out_clk | periph_dipsw_pio | ||
clk | |||
out_clk | periph_button_pio | ||
clk |
Parameters
|
Software Assignments(none) |
periph_periph_clk | out_clk | periph_periph_rst_in | |
clk | |||
rst_in | out_reset | ||
in_reset | |||
out_reset | periph_pb_cpu_0 | ||
reset | |||
out_reset | periph_led_pio | ||
reset | |||
out_reset | periph_dipsw_pio | ||
reset | |||
out_reset | periph_button_pio | ||
reset | |||
out_reset | periph_ILC | ||
reset_n |
Parameters
|
Software Assignments(none) |
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