subsys_jtg_mst

2018.12.27.15:21:32 Datasheet
Overview

Memory Map
f2sdram_m_0 f2sdram_m_1 f2sdram_m_2 fpga_m hps_m
 master  master  master  master  master

f2sdram_m_0

altera_jtag_avalon_master v18.1
jtag_clk out_clk   f2sdram_m_0
  clk
jtag_rst_in out_reset  
  clk_reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

f2sdram_m_1

altera_jtag_avalon_master v18.1
jtag_clk out_clk   f2sdram_m_1
  clk
jtag_rst_in out_reset  
  clk_reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

f2sdram_m_2

altera_jtag_avalon_master v18.1
jtag_clk out_clk   f2sdram_m_2
  clk
jtag_rst_in out_reset  
  clk_reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

fpga_m

altera_jtag_avalon_master v18.1
jtag_clk out_clk   fpga_m
  clk
jtag_rst_in out_reset  
  clk_reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

hps_m

altera_jtag_avalon_master v18.1
jtag_clk out_clk   hps_m
  clk
jtag_rst_in out_reset  
  clk_reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

jtag_clk

altera_clock_bridge v18.1


Parameters

generateLegacySim false
  

Software Assignments

(none)

jtag_rst_in

altera_reset_bridge v18.1
jtag_clk out_clk   jtag_rst_in
  clk
out_reset   fpga_m
  clk_reset
out_reset   hps_m
  clk_reset
out_reset   f2sdram_m_0
  clk_reset
out_reset   f2sdram_m_1
  clk_reset
out_reset   f2sdram_m_2
  clk_reset


Parameters

generateLegacySim false
  

Software Assignments

(none)
generation took 0.00 seconds rendering took 0.01 seconds