Hierarchy |
Input |
Constant Input |
Unused Input |
Floating Input |
Output |
Constant Output |
Unused Output |
Floating Output |
Bidir |
Constant Bidir |
Unused Bidir |
Input only Bidir |
Output only Bidir |
pulse_debug_reset |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
pulse_warm_reset |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
pulse_cold_reset |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
debounce_inst |
4 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|rst_controller_001|alt_rst_req_sync_uq1 |
2 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
soc_inst|rst_controller_001|alt_rst_sync_uq1 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|rst_controller_001 |
33 |
31 |
0 |
31 |
1 |
31 |
31 |
31 |
0 |
0 |
0 |
0 |
0 |
soc_inst|rst_controller|alt_rst_req_sync_uq1 |
2 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
soc_inst|rst_controller|alt_rst_sync_uq1 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|rst_controller |
33 |
31 |
0 |
31 |
2 |
31 |
31 |
31 |
0 |
0 |
0 |
0 |
0 |
soc_inst|irq_mapper_002 |
0 |
32 |
0 |
32 |
32 |
32 |
32 |
32 |
0 |
0 |
0 |
0 |
0 |
soc_inst|irq_mapper_001 |
3 |
29 |
0 |
29 |
32 |
29 |
29 |
29 |
0 |
0 |
0 |
0 |
0 |
soc_inst|irq_mapper |
5 |
0 |
2 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_3|avalon_st_adapter|error_adapter_0 |
262 |
1 |
2 |
1 |
261 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_3|avalon_st_adapter |
262 |
0 |
0 |
0 |
261 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_3|mux_pipeline_001|core |
119 |
0 |
0 |
0 |
117 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_3|mux_pipeline_001 |
121 |
2 |
0 |
2 |
117 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_3|mux_pipeline|core |
119 |
0 |
0 |
0 |
117 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_3|mux_pipeline |
121 |
2 |
0 |
2 |
117 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_3|agent_pipeline_001|core |
370 |
0 |
0 |
0 |
368 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_3|agent_pipeline_001 |
373 |
3 |
0 |
3 |
368 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_3|agent_pipeline|core |
371 |
0 |
0 |
0 |
369 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_3|agent_pipeline |
373 |
2 |
0 |
2 |
369 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_3|hps_0_f2h_sdram0_data_rsp_width_adapter |
374 |
3 |
2 |
3 |
117 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_3|hps_0_f2h_sdram0_data_cmd_width_adapter|uncompressor |
56 |
4 |
0 |
4 |
49 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_3|hps_0_f2h_sdram0_data_cmd_width_adapter |
122 |
16 |
0 |
16 |
369 |
16 |
16 |
16 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_3|rsp_mux |
119 |
0 |
2 |
0 |
117 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_3|rsp_demux |
119 |
1 |
2 |
1 |
117 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_3|cmd_mux |
119 |
0 |
2 |
0 |
117 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_3|cmd_demux |
119 |
1 |
2 |
1 |
117 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_3|router_001|the_default_decode |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_3|router_001 |
370 |
0 |
2 |
0 |
369 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_3|router|the_default_decode |
0 |
2 |
0 |
2 |
2 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_3|router |
118 |
2 |
3 |
2 |
117 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_3|hps_0_f2h_sdram0_data_agent_rsp_fifo |
410 |
39 |
0 |
39 |
369 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_3|hps_0_f2h_sdram0_data_agent|uncompressor |
56 |
1 |
0 |
1 |
54 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_3|hps_0_f2h_sdram0_data_agent |
1262 |
266 |
262 |
266 |
1334 |
266 |
266 |
266 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_3|f2sdram_only_master_master_agent |
194 |
41 |
81 |
41 |
150 |
41 |
41 |
41 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_3|hps_0_f2h_sdram0_data_translator |
601 |
4 |
5 |
4 |
583 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_3|f2sdram_only_master_master_translator |
116 |
13 |
2 |
13 |
109 |
13 |
13 |
13 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_3 |
332 |
0 |
1 |
0 |
359 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_2|mux_pipeline_003|core |
126 |
0 |
0 |
0 |
124 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_2|mux_pipeline_003 |
128 |
2 |
0 |
2 |
124 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_2|mux_pipeline_002|core |
126 |
0 |
0 |
0 |
124 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_2|mux_pipeline_002 |
128 |
2 |
0 |
2 |
124 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_2|mux_pipeline_001|core |
126 |
0 |
0 |
0 |
124 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_2|mux_pipeline_001 |
128 |
2 |
0 |
2 |
124 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_2|mux_pipeline|core |
126 |
0 |
0 |
0 |
124 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_2|mux_pipeline |
128 |
2 |
0 |
2 |
124 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_2|agent_pipeline_003|core |
160 |
0 |
0 |
0 |
158 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_2|agent_pipeline_003 |
163 |
3 |
0 |
3 |
158 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_2|agent_pipeline_002|core |
160 |
0 |
0 |
0 |
158 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_2|agent_pipeline_002 |
163 |
3 |
0 |
3 |
158 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_2|agent_pipeline_001|core |
162 |
0 |
0 |
0 |
160 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_2|agent_pipeline_001 |
164 |
2 |
0 |
2 |
160 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_2|agent_pipeline|core |
162 |
0 |
0 |
0 |
160 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_2|agent_pipeline |
164 |
2 |
0 |
2 |
160 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_2|limiter_pipeline_001|core |
126 |
0 |
0 |
0 |
124 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_2|limiter_pipeline_001 |
128 |
2 |
0 |
2 |
124 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_2|limiter_pipeline|core |
126 |
0 |
0 |
0 |
124 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_2|limiter_pipeline |
128 |
2 |
0 |
2 |
124 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_2|hps_0_f2h_axi_slave_rd_rsp_width_adapter |
165 |
3 |
2 |
3 |
124 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_2|hps_0_f2h_axi_slave_wr_rsp_width_adapter |
165 |
3 |
2 |
3 |
124 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_2|hps_0_f2h_axi_slave_rd_cmd_width_adapter|uncompressor |
58 |
4 |
0 |
4 |
44 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_2|hps_0_f2h_axi_slave_rd_cmd_width_adapter |
129 |
4 |
0 |
4 |
160 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_2|hps_0_f2h_axi_slave_wr_cmd_width_adapter|uncompressor |
58 |
4 |
0 |
4 |
44 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_2|hps_0_f2h_axi_slave_wr_cmd_width_adapter |
129 |
4 |
0 |
4 |
160 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_2|rsp_mux|arb|adder |
8 |
4 |
0 |
4 |
4 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_2|rsp_mux|arb |
6 |
0 |
4 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_2|rsp_mux |
249 |
0 |
0 |
0 |
125 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_2|rsp_demux_001 |
126 |
1 |
2 |
1 |
124 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_2|rsp_demux |
126 |
1 |
2 |
1 |
124 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_2|cmd_mux_001 |
126 |
0 |
2 |
0 |
124 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_2|cmd_mux |
126 |
0 |
2 |
0 |
124 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_2|cmd_demux |
127 |
4 |
2 |
4 |
247 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_2|hps_only_master_master_limiter |
250 |
1 |
1 |
1 |
248 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_2|router_002|the_default_decode |
0 |
2 |
0 |
2 |
2 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_2|router_002 |
160 |
0 |
2 |
0 |
160 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_2|router_001|the_default_decode |
0 |
2 |
0 |
2 |
2 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_2|router_001 |
160 |
0 |
2 |
0 |
160 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_2|router|the_default_decode |
0 |
5 |
0 |
5 |
5 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_2|router |
124 |
0 |
3 |
0 |
124 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_2|hps_0_f2h_axi_slave_agent|read_rsp_fifo |
200 |
41 |
0 |
41 |
157 |
41 |
41 |
41 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_2|hps_0_f2h_axi_slave_agent|write_rsp_fifo |
200 |
41 |
0 |
41 |
157 |
41 |
41 |
41 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_2|hps_0_f2h_axi_slave_agent|read_burst_uncompressor |
58 |
1 |
0 |
1 |
56 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_2|hps_0_f2h_axi_slave_agent|check_and_align_address_to_size |
46 |
9 |
2 |
9 |
35 |
9 |
9 |
9 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_2|hps_0_f2h_axi_slave_agent |
412 |
30 |
23 |
30 |
528 |
30 |
30 |
30 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_2|hps_only_master_master_agent |
201 |
47 |
88 |
47 |
156 |
47 |
47 |
47 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_2|hps_only_master_master_translator |
116 |
13 |
2 |
13 |
109 |
13 |
13 |
13 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_2 |
164 |
0 |
1 |
0 |
246 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|avalon_st_adapter_005|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|avalon_st_adapter_005 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|avalon_st_adapter_004|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|avalon_st_adapter_004 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|avalon_st_adapter_003|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|avalon_st_adapter_003 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|avalon_st_adapter_002|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|avalon_st_adapter_002 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|avalon_st_adapter_001|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|avalon_st_adapter_001 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|avalon_st_adapter|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|avalon_st_adapter |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|mux_pipeline_011|core |
104 |
0 |
0 |
0 |
102 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|mux_pipeline_011 |
106 |
2 |
0 |
2 |
102 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|mux_pipeline_010|core |
104 |
0 |
0 |
0 |
102 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|mux_pipeline_010 |
106 |
2 |
0 |
2 |
102 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|mux_pipeline_009|core |
104 |
0 |
0 |
0 |
102 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|mux_pipeline_009 |
106 |
2 |
0 |
2 |
102 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|mux_pipeline_008|core |
104 |
0 |
0 |
0 |
102 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|mux_pipeline_008 |
106 |
2 |
0 |
2 |
102 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|mux_pipeline_007|core |
104 |
0 |
0 |
0 |
102 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|mux_pipeline_007 |
106 |
2 |
0 |
2 |
102 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|mux_pipeline_006|core |
104 |
0 |
0 |
0 |
102 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|mux_pipeline_006 |
106 |
2 |
0 |
2 |
102 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|mux_pipeline_005|core |
104 |
0 |
0 |
0 |
102 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|mux_pipeline_005 |
106 |
2 |
0 |
2 |
102 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|mux_pipeline_004|core |
104 |
0 |
0 |
0 |
102 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|mux_pipeline_004 |
106 |
2 |
0 |
2 |
102 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|mux_pipeline_003|core |
104 |
0 |
0 |
0 |
102 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|mux_pipeline_003 |
106 |
2 |
0 |
2 |
102 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|mux_pipeline_002|core |
104 |
0 |
0 |
0 |
102 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|mux_pipeline_002 |
106 |
2 |
0 |
2 |
102 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|mux_pipeline_001|core |
104 |
0 |
0 |
0 |
102 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|mux_pipeline_001 |
106 |
2 |
0 |
2 |
102 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|mux_pipeline|core |
104 |
0 |
0 |
0 |
102 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|mux_pipeline |
106 |
2 |
0 |
2 |
102 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|agent_pipeline_011|core |
98 |
0 |
0 |
0 |
96 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|agent_pipeline_011 |
101 |
3 |
0 |
3 |
96 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|agent_pipeline_010|core |
104 |
0 |
0 |
0 |
102 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|agent_pipeline_010 |
106 |
2 |
0 |
2 |
102 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|agent_pipeline_009|core |
98 |
0 |
0 |
0 |
96 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|agent_pipeline_009 |
101 |
3 |
0 |
3 |
96 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|agent_pipeline_008|core |
104 |
0 |
0 |
0 |
102 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|agent_pipeline_008 |
106 |
2 |
0 |
2 |
102 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|agent_pipeline_007|core |
98 |
0 |
0 |
0 |
96 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|agent_pipeline_007 |
101 |
3 |
0 |
3 |
96 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|agent_pipeline_006|core |
104 |
0 |
0 |
0 |
102 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|agent_pipeline_006 |
106 |
2 |
0 |
2 |
102 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|agent_pipeline_005|core |
98 |
0 |
0 |
0 |
96 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|agent_pipeline_005 |
101 |
3 |
0 |
3 |
96 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|agent_pipeline_004|core |
104 |
0 |
0 |
0 |
102 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|agent_pipeline_004 |
106 |
2 |
0 |
2 |
102 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|agent_pipeline_003|core |
98 |
0 |
0 |
0 |
96 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|agent_pipeline_003 |
101 |
3 |
0 |
3 |
96 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|agent_pipeline_002|core |
104 |
0 |
0 |
0 |
102 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|agent_pipeline_002 |
106 |
2 |
0 |
2 |
102 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|agent_pipeline_001|core |
98 |
0 |
0 |
0 |
96 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|agent_pipeline_001 |
101 |
3 |
0 |
3 |
96 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|agent_pipeline|core |
104 |
0 |
0 |
0 |
102 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|agent_pipeline |
106 |
2 |
0 |
2 |
102 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|limiter_pipeline_001|core |
104 |
0 |
0 |
0 |
102 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|limiter_pipeline_001 |
106 |
2 |
0 |
2 |
102 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|limiter_pipeline|core |
104 |
0 |
0 |
0 |
102 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|limiter_pipeline |
106 |
2 |
0 |
2 |
102 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|rsp_mux|arb|adder |
24 |
12 |
0 |
12 |
12 |
12 |
12 |
12 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|rsp_mux|arb |
10 |
0 |
4 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|rsp_mux |
609 |
0 |
0 |
0 |
107 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|rsp_demux_005 |
104 |
1 |
2 |
1 |
102 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|rsp_demux_004 |
104 |
1 |
2 |
1 |
102 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|rsp_demux_003 |
104 |
1 |
2 |
1 |
102 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|rsp_demux_002 |
104 |
1 |
2 |
1 |
102 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|rsp_demux_001 |
104 |
1 |
2 |
1 |
102 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|rsp_demux |
104 |
1 |
2 |
1 |
102 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|cmd_mux_005 |
104 |
0 |
2 |
0 |
102 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|cmd_mux_004 |
104 |
0 |
2 |
0 |
102 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|cmd_mux_003 |
104 |
0 |
2 |
0 |
102 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|cmd_mux_002 |
104 |
0 |
2 |
0 |
102 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|cmd_mux_001 |
104 |
0 |
2 |
0 |
102 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|cmd_mux |
104 |
0 |
2 |
0 |
102 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|cmd_demux |
109 |
36 |
2 |
36 |
607 |
36 |
36 |
36 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|mm_bridge_0_m0_limiter |
206 |
0 |
0 |
0 |
204 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|router_006|the_default_decode |
0 |
6 |
0 |
6 |
6 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|router_006 |
98 |
0 |
2 |
0 |
102 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|router_005|the_default_decode |
0 |
6 |
0 |
6 |
6 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|router_005 |
98 |
0 |
2 |
0 |
102 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|router_004|the_default_decode |
0 |
6 |
0 |
6 |
6 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|router_004 |
98 |
0 |
2 |
0 |
102 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|router_003|the_default_decode |
0 |
6 |
0 |
6 |
6 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|router_003 |
98 |
0 |
2 |
0 |
102 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|router_002|the_default_decode |
0 |
6 |
0 |
6 |
6 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|router_002 |
98 |
0 |
2 |
0 |
102 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|router_001|the_default_decode |
0 |
6 |
0 |
6 |
6 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|router_001 |
98 |
0 |
2 |
0 |
102 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|router|the_default_decode |
0 |
9 |
0 |
9 |
9 |
9 |
9 |
9 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|router |
98 |
0 |
5 |
0 |
102 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|led_pio_s1_agent_rsp_fifo |
138 |
39 |
0 |
39 |
97 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|led_pio_s1_agent|uncompressor |
32 |
1 |
0 |
1 |
30 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|led_pio_s1_agent |
275 |
39 |
43 |
39 |
290 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|dipsw_pio_s1_agent_rsp_fifo |
138 |
39 |
0 |
39 |
97 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|dipsw_pio_s1_agent|uncompressor |
32 |
1 |
0 |
1 |
30 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|dipsw_pio_s1_agent |
275 |
39 |
43 |
39 |
290 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|button_pio_s1_agent_rsp_fifo |
138 |
39 |
0 |
39 |
97 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|button_pio_s1_agent|uncompressor |
32 |
1 |
0 |
1 |
30 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|button_pio_s1_agent |
275 |
39 |
43 |
39 |
290 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|sysid_qsys_control_slave_agent_rsp_fifo |
138 |
39 |
0 |
39 |
97 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|sysid_qsys_control_slave_agent|uncompressor |
32 |
1 |
0 |
1 |
30 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|sysid_qsys_control_slave_agent |
275 |
39 |
43 |
39 |
290 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|ilc_avalon_slave_agent_rsp_fifo |
138 |
39 |
0 |
39 |
97 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|ilc_avalon_slave_agent|uncompressor |
32 |
1 |
0 |
1 |
30 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|ilc_avalon_slave_agent |
275 |
39 |
43 |
39 |
290 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|jtag_uart_avalon_jtag_slave_agent_rsp_fifo |
138 |
39 |
0 |
39 |
97 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|jtag_uart_avalon_jtag_slave_agent|uncompressor |
32 |
1 |
0 |
1 |
30 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|jtag_uart_avalon_jtag_slave_agent |
275 |
39 |
43 |
39 |
290 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|mm_bridge_0_m0_agent |
165 |
35 |
70 |
35 |
130 |
35 |
35 |
35 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|led_pio_s1_translator |
101 |
6 |
18 |
6 |
71 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|dipsw_pio_s1_translator |
101 |
6 |
19 |
6 |
70 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|button_pio_s1_translator |
101 |
6 |
19 |
6 |
70 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|sysid_qsys_control_slave_translator |
101 |
6 |
17 |
6 |
35 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|ilc_avalon_slave_translator |
101 |
6 |
12 |
6 |
74 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|jtag_uart_avalon_jtag_slave_translator |
101 |
5 |
20 |
5 |
70 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1|mm_bridge_0_m0_translator |
102 |
10 |
2 |
10 |
95 |
10 |
10 |
10 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_1 |
253 |
0 |
0 |
0 |
220 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|avalon_st_adapter_001|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|avalon_st_adapter_001 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|avalon_st_adapter|error_adapter_0 |
14 |
1 |
2 |
1 |
13 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|avalon_st_adapter |
14 |
0 |
0 |
0 |
13 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|mux_pipeline_011|core |
138 |
0 |
0 |
0 |
136 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|mux_pipeline_011 |
140 |
2 |
0 |
2 |
136 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|mux_pipeline_010|core |
138 |
0 |
0 |
0 |
136 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|mux_pipeline_010 |
140 |
2 |
0 |
2 |
136 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|mux_pipeline_009|core |
138 |
0 |
0 |
0 |
136 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|mux_pipeline_009 |
140 |
2 |
0 |
2 |
136 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|mux_pipeline_008|core |
138 |
0 |
0 |
0 |
136 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|mux_pipeline_008 |
140 |
2 |
0 |
2 |
136 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|mux_pipeline_007|core |
174 |
0 |
0 |
0 |
172 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|mux_pipeline_007 |
176 |
2 |
0 |
2 |
172 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|mux_pipeline_006|core |
174 |
0 |
0 |
0 |
172 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|mux_pipeline_006 |
176 |
2 |
0 |
2 |
172 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|mux_pipeline_005|core |
138 |
0 |
0 |
0 |
136 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|mux_pipeline_005 |
140 |
2 |
0 |
2 |
136 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|mux_pipeline_004|core |
138 |
0 |
0 |
0 |
136 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|mux_pipeline_004 |
140 |
2 |
0 |
2 |
136 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|mux_pipeline_003|core |
138 |
0 |
0 |
0 |
136 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|mux_pipeline_003 |
140 |
2 |
0 |
2 |
136 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|mux_pipeline_002|core |
111 |
0 |
0 |
0 |
109 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|mux_pipeline_002 |
113 |
2 |
0 |
2 |
109 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|mux_pipeline_001|core |
111 |
0 |
0 |
0 |
109 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|mux_pipeline_001 |
113 |
2 |
0 |
2 |
109 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|mux_pipeline|core |
111 |
0 |
0 |
0 |
109 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|mux_pipeline |
113 |
2 |
0 |
2 |
109 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|agent_pipeline_003|core |
133 |
0 |
0 |
0 |
131 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|agent_pipeline_003 |
136 |
3 |
0 |
3 |
131 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|agent_pipeline_002|core |
138 |
0 |
0 |
0 |
136 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|agent_pipeline_002 |
140 |
2 |
0 |
2 |
136 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|agent_pipeline_001|core |
106 |
0 |
0 |
0 |
104 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|agent_pipeline_001 |
109 |
3 |
0 |
3 |
104 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|agent_pipeline|core |
111 |
0 |
0 |
0 |
109 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|agent_pipeline |
113 |
2 |
0 |
2 |
109 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|limiter_pipeline_001|core |
138 |
0 |
0 |
0 |
136 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|limiter_pipeline_001 |
140 |
2 |
0 |
2 |
136 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|limiter_pipeline|core |
138 |
0 |
0 |
0 |
136 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|limiter_pipeline |
140 |
2 |
0 |
2 |
136 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter|uncompressor |
58 |
4 |
0 |
4 |
44 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|onchip_memory2_0_s1_to_fpga_only_master_master_rsp_width_adapter |
114 |
3 |
0 |
3 |
136 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|onchip_memory2_0_s1_to_hps_0_h2f_axi_master_rd_rsp_width_adapter|uncompressor |
58 |
4 |
0 |
4 |
44 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|onchip_memory2_0_s1_to_hps_0_h2f_axi_master_rd_rsp_width_adapter |
114 |
3 |
0 |
3 |
172 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|onchip_memory2_0_s1_to_hps_0_h2f_axi_master_wr_rsp_width_adapter|uncompressor |
58 |
4 |
0 |
4 |
44 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|onchip_memory2_0_s1_to_hps_0_h2f_axi_master_wr_rsp_width_adapter |
114 |
3 |
0 |
3 |
172 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter|check_and_align_address_to_size |
46 |
9 |
2 |
9 |
34 |
9 |
9 |
9 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|fpga_only_master_master_to_onchip_memory2_0_s1_cmd_width_adapter |
141 |
3 |
2 |
3 |
109 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|hps_0_h2f_axi_master_rd_to_onchip_memory2_0_s1_cmd_width_adapter|check_and_align_address_to_size |
46 |
9 |
2 |
9 |
35 |
9 |
9 |
9 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|hps_0_h2f_axi_master_rd_to_onchip_memory2_0_s1_cmd_width_adapter |
177 |
3 |
3 |
3 |
109 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|hps_0_h2f_axi_master_wr_to_onchip_memory2_0_s1_cmd_width_adapter|check_and_align_address_to_size |
46 |
9 |
2 |
9 |
35 |
9 |
9 |
9 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|hps_0_h2f_axi_master_wr_to_onchip_memory2_0_s1_cmd_width_adapter |
177 |
3 |
3 |
3 |
109 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|rsp_mux_004 |
138 |
0 |
2 |
0 |
136 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|rsp_mux_003 |
138 |
0 |
2 |
0 |
136 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|rsp_mux_002|arb|adder |
8 |
4 |
0 |
4 |
4 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|rsp_mux_002|arb |
6 |
0 |
4 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|rsp_mux_002 |
273 |
0 |
0 |
0 |
137 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|rsp_mux_001 |
174 |
0 |
2 |
0 |
172 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|rsp_mux |
174 |
0 |
2 |
0 |
172 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|rsp_demux_001 |
140 |
9 |
2 |
9 |
406 |
9 |
9 |
9 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|rsp_demux |
113 |
9 |
2 |
9 |
325 |
9 |
9 |
9 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|cmd_mux_001|arb|adder |
12 |
3 |
0 |
3 |
6 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|cmd_mux_001|arb |
7 |
0 |
1 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|cmd_mux_001 |
408 |
0 |
0 |
0 |
138 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|cmd_mux|arb|adder |
12 |
3 |
0 |
3 |
6 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|cmd_mux|arb |
7 |
0 |
1 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|cmd_mux |
327 |
0 |
0 |
0 |
111 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|cmd_demux_004 |
138 |
1 |
2 |
1 |
136 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|cmd_demux_003 |
138 |
1 |
2 |
1 |
136 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|cmd_demux_002 |
139 |
4 |
2 |
4 |
271 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|cmd_demux_001 |
174 |
1 |
2 |
1 |
172 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|cmd_demux |
174 |
1 |
2 |
1 |
172 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|mm_bridge_0_s0_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|dc_sub|subtract |
19 |
1 |
0 |
1 |
9 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|mm_bridge_0_s0_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|dc_sub |
18 |
2 |
0 |
2 |
9 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|mm_bridge_0_s0_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|db_sub|subtract |
19 |
1 |
0 |
1 |
9 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|mm_bridge_0_s0_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|db_sub |
18 |
2 |
0 |
2 |
9 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|mm_bridge_0_s0_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|da_sub|subtract |
19 |
1 |
0 |
1 |
9 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|mm_bridge_0_s0_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|da_sub |
18 |
2 |
0 |
2 |
9 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|mm_bridge_0_s0_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|bc_sub|subtract |
19 |
1 |
0 |
1 |
9 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|mm_bridge_0_s0_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|bc_sub |
18 |
2 |
0 |
2 |
9 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|mm_bridge_0_s0_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ac_sub|subtract |
19 |
1 |
0 |
1 |
9 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|mm_bridge_0_s0_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ac_sub |
18 |
2 |
0 |
2 |
9 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|mm_bridge_0_s0_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ab_sub|subtract |
19 |
1 |
0 |
1 |
9 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|mm_bridge_0_s0_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ab_sub |
18 |
2 |
0 |
2 |
9 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|mm_bridge_0_s0_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min |
35 |
0 |
2 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|mm_bridge_0_s0_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_burstwrap_increment |
8 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|mm_bridge_0_s0_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size |
40 |
5 |
0 |
5 |
34 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|mm_bridge_0_s0_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter |
138 |
0 |
0 |
0 |
136 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|mm_bridge_0_s0_burst_adapter |
138 |
0 |
0 |
0 |
136 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|dc_sub|subtract |
19 |
1 |
0 |
1 |
9 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|dc_sub |
18 |
2 |
0 |
2 |
9 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|db_sub|subtract |
19 |
1 |
0 |
1 |
9 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|db_sub |
18 |
2 |
0 |
2 |
9 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|da_sub|subtract |
19 |
1 |
0 |
1 |
9 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|da_sub |
18 |
2 |
0 |
2 |
9 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|bc_sub|subtract |
19 |
1 |
0 |
1 |
9 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|bc_sub |
18 |
2 |
0 |
2 |
9 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ac_sub|subtract |
19 |
1 |
0 |
1 |
9 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ac_sub |
18 |
2 |
0 |
2 |
9 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ab_sub|subtract |
19 |
1 |
0 |
1 |
9 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min|ab_sub |
18 |
2 |
0 |
2 |
9 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_min |
35 |
0 |
2 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|the_burstwrap_increment |
8 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size |
40 |
5 |
3 |
5 |
32 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter |
111 |
0 |
0 |
0 |
109 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|onchip_memory2_0_s1_burst_adapter |
111 |
0 |
0 |
0 |
109 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|fpga_only_master_master_limiter |
274 |
0 |
0 |
0 |
272 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|router_006|the_default_decode |
0 |
5 |
0 |
5 |
5 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|router_006 |
133 |
0 |
2 |
0 |
136 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|router_005|the_default_decode |
0 |
10 |
0 |
10 |
10 |
10 |
10 |
10 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|router_005 |
106 |
0 |
2 |
0 |
109 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|router_004|the_default_decode |
0 |
7 |
0 |
7 |
7 |
7 |
7 |
7 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|router_004 |
133 |
7 |
4 |
7 |
136 |
7 |
7 |
7 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|router_003|the_default_decode |
0 |
7 |
0 |
7 |
7 |
7 |
7 |
7 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|router_003 |
133 |
7 |
4 |
7 |
136 |
7 |
7 |
7 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|router_002|the_default_decode |
0 |
7 |
0 |
7 |
7 |
7 |
7 |
7 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|router_002 |
133 |
0 |
4 |
0 |
136 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|router_001|the_default_decode |
0 |
7 |
0 |
7 |
7 |
7 |
7 |
7 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|router_001 |
169 |
7 |
4 |
7 |
172 |
7 |
7 |
7 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|router|the_default_decode |
0 |
7 |
0 |
7 |
7 |
7 |
7 |
7 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|router |
169 |
7 |
4 |
7 |
172 |
7 |
7 |
7 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|mm_bridge_0_s0_agent_rdata_fifo |
79 |
41 |
0 |
41 |
36 |
41 |
41 |
41 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|mm_bridge_0_s0_agent_rsp_fifo |
173 |
39 |
0 |
39 |
132 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|mm_bridge_0_s0_agent|uncompressor |
58 |
1 |
0 |
1 |
56 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|mm_bridge_0_s0_agent |
344 |
39 |
42 |
39 |
374 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|onchip_memory2_0_s1_agent_rdata_fifo |
55 |
41 |
0 |
41 |
12 |
41 |
41 |
41 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|onchip_memory2_0_s1_agent_rsp_fifo |
146 |
39 |
0 |
39 |
105 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|onchip_memory2_0_s1_agent|uncompressor |
58 |
1 |
0 |
1 |
56 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|onchip_memory2_0_s1_agent |
242 |
13 |
18 |
13 |
267 |
13 |
13 |
13 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|hps_0_h2f_lw_axi_master_agent|align_address_to_size |
50 |
11 |
1 |
11 |
34 |
11 |
11 |
11 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|hps_0_h2f_lw_axi_master_agent |
449 |
99 |
219 |
99 |
328 |
99 |
99 |
99 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|fpga_only_master_master_agent |
213 |
56 |
104 |
56 |
165 |
56 |
56 |
56 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size |
50 |
2 |
1 |
2 |
35 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|hps_0_h2f_axi_master_agent |
575 |
126 |
259 |
126 |
432 |
126 |
126 |
126 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|mm_bridge_0_s0_translator |
115 |
4 |
14 |
4 |
92 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|onchip_memory2_0_s1_translator |
62 |
7 |
16 |
7 |
37 |
7 |
7 |
7 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0|fpga_only_master_master_translator |
116 |
13 |
2 |
13 |
109 |
13 |
13 |
13 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_interconnect_0 |
482 |
0 |
1 |
0 |
283 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|sysid_qsys |
3 |
13 |
2 |
13 |
32 |
13 |
13 |
13 |
0 |
0 |
0 |
0 |
0 |
soc_inst|onchip_memory2_0|the_altsyncram|auto_generated|mux2 |
67 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|onchip_memory2_0|the_altsyncram|auto_generated|decode3 |
4 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|onchip_memory2_0|the_altsyncram|auto_generated |
27 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|onchip_memory2_0 |
31 |
1 |
1 |
1 |
8 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
soc_inst|mm_bridge_0 |
96 |
2 |
0 |
2 |
92 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
soc_inst|led_pio |
43 |
0 |
28 |
0 |
36 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|jtag_uart|the_soc_system_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|wr_ptr |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|jtag_uart|the_soc_system_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|rd_ptr_count |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|jtag_uart|the_soc_system_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|FIFOram |
24 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|jtag_uart|the_soc_system_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|fifo_state|count_usedw |
5 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|jtag_uart|the_soc_system_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|fifo_state |
5 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|jtag_uart|the_soc_system_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo |
13 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|jtag_uart|the_soc_system_jtag_uart_scfifo_r|rfifo|auto_generated |
12 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|jtag_uart|the_soc_system_jtag_uart_scfifo_r |
13 |
0 |
1 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|jtag_uart|the_soc_system_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|wr_ptr |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|jtag_uart|the_soc_system_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|rd_ptr_count |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|jtag_uart|the_soc_system_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|FIFOram |
24 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|jtag_uart|the_soc_system_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|fifo_state|count_usedw |
5 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|jtag_uart|the_soc_system_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|fifo_state |
5 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|jtag_uart|the_soc_system_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo |
13 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|jtag_uart|the_soc_system_jtag_uart_scfifo_w|wfifo|auto_generated |
12 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|jtag_uart|the_soc_system_jtag_uart_scfifo_w |
12 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|jtag_uart |
38 |
10 |
23 |
10 |
34 |
10 |
10 |
10 |
0 |
0 |
0 |
0 |
0 |
soc_inst|in_system_sources_probes_0 |
2 |
1 |
0 |
1 |
3 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
soc_inst|hps_only_master|rst_controller|alt_rst_req_sync_uq1 |
2 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
soc_inst|hps_only_master|rst_controller|alt_rst_sync_uq1 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|hps_only_master|rst_controller |
33 |
31 |
0 |
31 |
1 |
31 |
31 |
31 |
0 |
0 |
0 |
0 |
0 |
soc_inst|hps_only_master|p2b_adapter |
14 |
8 |
2 |
8 |
20 |
8 |
8 |
8 |
0 |
0 |
0 |
0 |
0 |
soc_inst|hps_only_master|b2p_adapter |
22 |
0 |
2 |
0 |
12 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|hps_only_master|transacto|p2m |
48 |
0 |
0 |
0 |
82 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|hps_only_master|transacto |
48 |
0 |
0 |
0 |
82 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|hps_only_master|p2b |
22 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|hps_only_master|b2p |
12 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|hps_only_master|fifo |
53 |
41 |
0 |
41 |
10 |
41 |
41 |
41 |
0 |
0 |
0 |
0 |
0 |
soc_inst|hps_only_master|timing_adt |
12 |
0 |
3 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|hps_only_master|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|source_crosser|crosser |
4 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
soc_inst|hps_only_master|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|source_crosser |
13 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|hps_only_master|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|sink_crosser|output_stage |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|hps_only_master|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|sink_crosser|out_to_in_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|hps_only_master|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|sink_crosser|in_to_out_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|hps_only_master|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|sink_crosser |
14 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|hps_only_master|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|jtag_streaming|idle_inserter |
12 |
1 |
0 |
1 |
10 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
soc_inst|hps_only_master|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|jtag_streaming|idle_remover |
12 |
2 |
0 |
2 |
10 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
soc_inst|hps_only_master|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|jtag_streaming |
20 |
1 |
0 |
1 |
16 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
soc_inst|hps_only_master|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming |
19 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|hps_only_master|jtag_phy_embedded_in_jtag_master|node |
4 |
3 |
0 |
3 |
8 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
soc_inst|hps_only_master|jtag_phy_embedded_in_jtag_master |
38 |
27 |
0 |
27 |
11 |
27 |
27 |
27 |
0 |
0 |
0 |
0 |
0 |
soc_inst|hps_only_master |
36 |
0 |
0 |
0 |
70 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|hps_0|hps_io|border|hps_sdram_inst|dll |
2 |
0 |
0 |
0 |
7 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|hps_0|hps_io|border|hps_sdram_inst|oct |
1 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|hps_0|hps_io|border|hps_sdram_inst|c0 |
228 |
173 |
8 |
173 |
280 |
173 |
173 |
173 |
0 |
0 |
0 |
0 |
0 |
soc_inst|hps_0|hps_io|border|hps_sdram_inst|seq |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_inst |
135 |
1 |
3 |
1 |
36 |
1 |
1 |
1 |
10 |
0 |
0 |
0 |
0 |
soc_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[4].ubidir_dq_dqs |
135 |
0 |
0 |
0 |
36 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
soc_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst |
135 |
1 |
3 |
1 |
36 |
1 |
1 |
1 |
10 |
0 |
0 |
0 |
0 |
soc_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs |
135 |
0 |
0 |
0 |
36 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
soc_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst |
135 |
1 |
3 |
1 |
36 |
1 |
1 |
1 |
10 |
0 |
0 |
0 |
0 |
soc_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs |
135 |
0 |
0 |
0 |
36 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
soc_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst |
135 |
1 |
3 |
1 |
36 |
1 |
1 |
1 |
10 |
0 |
0 |
0 |
0 |
soc_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs |
135 |
0 |
0 |
0 |
36 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
soc_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst |
135 |
1 |
3 |
1 |
36 |
1 |
1 |
1 |
10 |
0 |
0 |
0 |
0 |
soc_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs |
135 |
0 |
0 |
0 |
36 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
soc_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|clock_gen[0].uclk_generator |
1 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|clock_gen[0].umem_ck_pad|auto_generated |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|ureset_n_pad |
7 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
soc_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|ucmd_pad |
37 |
1 |
0 |
1 |
6 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
soc_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|ubank_pad |
19 |
1 |
0 |
1 |
3 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
soc_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|uaddress_pad |
91 |
1 |
0 |
1 |
15 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
soc_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[24].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[23].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[22].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[21].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[20].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[19].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[18].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[17].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[16].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[15].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[14].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[13].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[12].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[11].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[10].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[9].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[8].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[7].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[6].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[5].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[4].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[3].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[2].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[1].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads|address_gen[0].acv_ac_ldc |
10 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|uaddr_cmd_pads |
118 |
0 |
5 |
0 |
27 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads |
644 |
25 |
44 |
25 |
222 |
25 |
25 |
25 |
50 |
0 |
0 |
0 |
0 |
soc_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|memphy_ldc |
10 |
0 |
1 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy |
986 |
1 |
2 |
1 |
368 |
1 |
1 |
1 |
50 |
0 |
0 |
0 |
0 |
soc_inst|hps_0|hps_io|border|hps_sdram_inst|p0 |
878 |
545 |
0 |
545 |
131 |
545 |
545 |
545 |
50 |
0 |
0 |
0 |
0 |
soc_inst|hps_0|hps_io|border|hps_sdram_inst|pll |
2 |
1 |
2 |
1 |
12 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
soc_inst|hps_0|hps_io|border|hps_sdram_inst |
1 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
50 |
0 |
0 |
0 |
0 |
soc_inst|hps_0|hps_io|border |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|hps_0|hps_io |
13 |
0 |
0 |
0 |
57 |
0 |
0 |
0 |
76 |
0 |
0 |
0 |
0 |
soc_inst|hps_0|fpga_interfaces |
800 |
0 |
0 |
0 |
715 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|hps_0 |
813 |
0 |
0 |
0 |
772 |
0 |
0 |
0 |
76 |
0 |
0 |
0 |
0 |
soc_inst|fpga_only_master|rst_controller|alt_rst_req_sync_uq1 |
2 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
soc_inst|fpga_only_master|rst_controller|alt_rst_sync_uq1 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|fpga_only_master|rst_controller |
33 |
31 |
0 |
31 |
1 |
31 |
31 |
31 |
0 |
0 |
0 |
0 |
0 |
soc_inst|fpga_only_master|p2b_adapter |
14 |
8 |
2 |
8 |
20 |
8 |
8 |
8 |
0 |
0 |
0 |
0 |
0 |
soc_inst|fpga_only_master|b2p_adapter |
22 |
0 |
2 |
0 |
12 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|fpga_only_master|transacto|p2m |
48 |
0 |
0 |
0 |
82 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|fpga_only_master|transacto |
48 |
0 |
0 |
0 |
82 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|fpga_only_master|p2b |
22 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|fpga_only_master|b2p |
12 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|fpga_only_master|fifo |
53 |
41 |
0 |
41 |
10 |
41 |
41 |
41 |
0 |
0 |
0 |
0 |
0 |
soc_inst|fpga_only_master|timing_adt |
12 |
0 |
3 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|fpga_only_master|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|source_crosser|crosser |
4 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
soc_inst|fpga_only_master|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|source_crosser |
13 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|fpga_only_master|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|sink_crosser|output_stage |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|fpga_only_master|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|sink_crosser|out_to_in_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|fpga_only_master|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|sink_crosser|in_to_out_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|fpga_only_master|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|sink_crosser |
14 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|fpga_only_master|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|jtag_streaming|idle_inserter |
12 |
1 |
0 |
1 |
10 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
soc_inst|fpga_only_master|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|jtag_streaming|idle_remover |
12 |
2 |
0 |
2 |
10 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
soc_inst|fpga_only_master|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|jtag_streaming |
20 |
1 |
0 |
1 |
16 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
soc_inst|fpga_only_master|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming |
19 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|fpga_only_master|jtag_phy_embedded_in_jtag_master|node |
4 |
3 |
0 |
3 |
8 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
soc_inst|fpga_only_master|jtag_phy_embedded_in_jtag_master |
38 |
27 |
0 |
27 |
11 |
27 |
27 |
27 |
0 |
0 |
0 |
0 |
0 |
soc_inst|fpga_only_master |
36 |
0 |
0 |
0 |
70 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|f2sdram_only_master|rst_controller|alt_rst_req_sync_uq1 |
2 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
soc_inst|f2sdram_only_master|rst_controller|alt_rst_sync_uq1 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|f2sdram_only_master|rst_controller |
33 |
31 |
0 |
31 |
1 |
31 |
31 |
31 |
0 |
0 |
0 |
0 |
0 |
soc_inst|f2sdram_only_master|p2b_adapter |
14 |
8 |
2 |
8 |
20 |
8 |
8 |
8 |
0 |
0 |
0 |
0 |
0 |
soc_inst|f2sdram_only_master|b2p_adapter |
22 |
0 |
2 |
0 |
12 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|f2sdram_only_master|transacto|p2m |
48 |
0 |
0 |
0 |
82 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|f2sdram_only_master|transacto |
48 |
0 |
0 |
0 |
82 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|f2sdram_only_master|p2b |
22 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|f2sdram_only_master|b2p |
12 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|f2sdram_only_master|fifo |
53 |
41 |
0 |
41 |
10 |
41 |
41 |
41 |
0 |
0 |
0 |
0 |
0 |
soc_inst|f2sdram_only_master|timing_adt |
12 |
0 |
3 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|f2sdram_only_master|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|source_crosser|crosser |
4 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
soc_inst|f2sdram_only_master|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|source_crosser |
13 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|f2sdram_only_master|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|sink_crosser|output_stage |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|f2sdram_only_master|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|sink_crosser|out_to_in_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|f2sdram_only_master|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|sink_crosser|in_to_out_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|f2sdram_only_master|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|sink_crosser |
14 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|f2sdram_only_master|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|jtag_streaming|idle_inserter |
12 |
1 |
0 |
1 |
10 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
soc_inst|f2sdram_only_master|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|jtag_streaming|idle_remover |
12 |
2 |
0 |
2 |
10 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
soc_inst|f2sdram_only_master|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming|jtag_streaming |
20 |
1 |
0 |
1 |
16 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
soc_inst|f2sdram_only_master|jtag_phy_embedded_in_jtag_master|normal.jtag_dc_streaming |
19 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|f2sdram_only_master|jtag_phy_embedded_in_jtag_master|node |
4 |
3 |
0 |
3 |
8 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
soc_inst|f2sdram_only_master|jtag_phy_embedded_in_jtag_master |
38 |
27 |
0 |
27 |
11 |
27 |
27 |
27 |
0 |
0 |
0 |
0 |
0 |
soc_inst|f2sdram_only_master |
36 |
0 |
0 |
0 |
70 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|dipsw_pio |
42 |
0 |
28 |
0 |
33 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|button_pio |
40 |
0 |
30 |
0 |
33 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|ilc|state_machine[2].state_machine_counter |
6 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|ilc|state_machine[1].state_machine_counter |
6 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|ilc|state_machine[0].state_machine_counter |
6 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|ilc|irq_detector_cicuit[2].irq_detector |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|ilc|irq_detector_cicuit[1].irq_detector |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|ilc|irq_detector_cicuit[0].irq_detector |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst|ilc |
45 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
soc_inst |
56 |
18 |
0 |
18 |
65 |
18 |
18 |
18 |
76 |
0 |
0 |
0 |
0 |