ghrd_10as066n2_emif_hps

2017.05.02.01:00:28 Datasheet
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emif_hps

altera_emif_a10_hps v17.0


Parameters

SYS_INFO_DEVICE_FAMILY ARRIA10
SYS_INFO_DEVICE 10AS066N3F40E2SG
SYS_INFO_DEVICE_SPEEDGRADE 2
FAMILY_ENUM FAMILY_ARRIA10_HPS
TRAIT_SUPPORTS_VID 0
PROTOCOL_ENUM PROTOCOL_DDR4
IS_ED_SLAVE false
INTERNAL_TESTING_MODE false
CAL_DEBUG_CLOCK_FREQUENCY 50000000
SYS_INFO_UNIQUE_ID ghrd_10as066n2_emif_hps_emif_hps
PREV_PROTOCOL_ENUM PROTOCOL_DDR4
PHY_FPGA_SPEEDGRADE_GUI E2 (Production) - change device under 'View'->'Device Family'
PHY_TARGET_SPEEDGRADE E2
PHY_TARGET_IS_ES false
PHY_TARGET_IS_ES2 false
PHY_TARGET_IS_ES3 false
PHY_TARGET_IS_PRODUCTION true
PHY_CONFIG_ENUM CONFIG_PHY_AND_HARD_CTRL
PHY_PING_PONG_EN false
PHY_RATE_ENUM RATE_HALF
PHY_MEM_CLK_FREQ_MHZ 1066.667
PHY_REF_CLK_FREQ_MHZ 133.333
PHY_REF_CLK_JITTER_PS 10.0
PHY_CORE_CLKS_SHARING_ENUM CORE_CLKS_SHARING_DISABLED
PHY_CALIBRATED_OCT true
PHY_AC_CALIBRATED_OCT true
PHY_CK_CALIBRATED_OCT true
PHY_DATA_CALIBRATED_OCT true
PHY_RZQ 240
PHY_HPS_ENABLE_EARLY_RELEASE true
PHY_USER_PERIODIC_OCT_RECAL_ENUM PERIODIC_OCT_RECAL_AUTO
PLL_ADD_EXTRA_CLKS false
PLL_USER_NUM_OF_EXTRA_CLKS 0
PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_0 0.0
PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_0 0.0
PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_0 0.0
PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_0 ps
PLL_EXTRA_CLK_DESIRED_PHASE_GUI_0 0.0
PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_0 0.0
PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_0 50.0
PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_0 50.0
PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_0 50.0
PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_1 0.0
PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_1 0.0
PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_1 0.0
PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_1 ps
PLL_EXTRA_CLK_DESIRED_PHASE_GUI_1 0.0
PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_1 0.0
PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_1 50.0
PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_1 50.0
PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_1 50.0
PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_2 0.0
PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_2 0.0
PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_2 0.0
PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_2 ps
PLL_EXTRA_CLK_DESIRED_PHASE_GUI_2 0.0
PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_2 0.0
PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_2 50.0
PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_2 50.0
PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_2 50.0
PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_3 0.0
PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_3 0.0
PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_3 0.0
PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_3 ps
PLL_EXTRA_CLK_DESIRED_PHASE_GUI_3 0.0
PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_3 0.0
PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_3 50.0
PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_3 50.0
PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_3 50.0
PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_4 0.0
PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_4 0.0
PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_4 0.0
PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_4 ps
PLL_EXTRA_CLK_DESIRED_PHASE_GUI_4 0.0
PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_4 0.0
PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_4 50.0
PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_4 50.0
PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_4 50.0
PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_5 0.0
PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_5 0.0
PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_5 0.0
PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_5 ps
PLL_EXTRA_CLK_DESIRED_PHASE_GUI_5 0.0
PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_5 0.0
PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_5 50.0
PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_5 50.0
PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_5 50.0
PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_6 0.0
PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_6 0.0
PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_6 0.0
PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_6 ps
PLL_EXTRA_CLK_DESIRED_PHASE_GUI_6 0.0
PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_6 0.0
PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_6 50.0
PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_6 50.0
PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_6 50.0
PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_7 0.0
PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_7 0.0
PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_7 0.0
PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_7 ps
PLL_EXTRA_CLK_DESIRED_PHASE_GUI_7 0.0
PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_7 0.0
PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_7 50.0
PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_7 50.0
PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_7 50.0
PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_8 0.0
PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_8 0.0
PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_8 0.0
PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_8 ps
PLL_EXTRA_CLK_DESIRED_PHASE_GUI_8 0.0
PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_8 0.0
PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_8 50.0
PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_8 50.0
PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_8 50.0
PLL_VCO_CLK_FREQ_MHZ 1066.667
PLL_NUM_OF_EXTRA_CLKS 0
PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_0 0.0
PLL_EXTRA_CLK_ACTUAL_PHASE_PS_0 0.0
PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_1 0.0
PLL_EXTRA_CLK_ACTUAL_PHASE_PS_1 0.0
PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_2 0.0
PLL_EXTRA_CLK_ACTUAL_PHASE_PS_2 0.0
PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_3 0.0
PLL_EXTRA_CLK_ACTUAL_PHASE_PS_3 0.0
PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_4 0.0
PLL_EXTRA_CLK_ACTUAL_PHASE_PS_4 0.0
PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_5 1066.667
PLL_EXTRA_CLK_ACTUAL_PHASE_PS_5 0.0
PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_6 1066.667
PLL_EXTRA_CLK_ACTUAL_PHASE_PS_6 0.0
PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_7 1066.667
PLL_EXTRA_CLK_ACTUAL_PHASE_PS_7 0.0
PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_8 1066.667
PLL_EXTRA_CLK_ACTUAL_PHASE_PS_8 0.0
PHY_DDR3_CONFIG_ENUM CONFIG_PHY_AND_HARD_CTRL
PHY_DDR3_USER_PING_PONG_EN false
PHY_DDR3_MEM_CLK_FREQ_MHZ 1066.667
PHY_DDR3_DEFAULT_REF_CLK_FREQ true
PHY_DDR3_USER_REF_CLK_FREQ_MHZ -1.0
PHY_DDR3_REF_CLK_JITTER_PS 10.0
PHY_DDR3_RATE_ENUM RATE_HALF
PHY_DDR3_CORE_CLKS_SHARING_ENUM CORE_CLKS_SHARING_DISABLED
PHY_DDR3_IO_VOLTAGE 1.5
PHY_DDR3_DEFAULT_IO true
PHY_DDR3_HPS_ENABLE_EARLY_RELEASE false
PHY_DDR3_USER_PERIODIC_OCT_RECAL_ENUM PERIODIC_OCT_RECAL_AUTO
PHY_DDR3_REF_CLK_FREQ_MHZ -1.0
PHY_DDR3_PING_PONG_EN false
PHY_DDR3_USER_AC_IO_STD_ENUM unset
PHY_DDR3_USER_AC_MODE_ENUM unset
PHY_DDR3_USER_AC_SLEW_RATE_ENUM SLEW_RATE_FAST
PHY_DDR3_USER_CK_IO_STD_ENUM unset
PHY_DDR3_USER_CK_MODE_ENUM unset
PHY_DDR3_USER_CK_SLEW_RATE_ENUM SLEW_RATE_FAST
PHY_DDR3_USER_DATA_IO_STD_ENUM unset
PHY_DDR3_USER_DATA_OUT_MODE_ENUM unset
PHY_DDR3_USER_DATA_IN_MODE_ENUM unset
PHY_DDR3_USER_AUTO_STARTING_VREFIN_EN true
PHY_DDR3_USER_STARTING_VREFIN 70.0
PHY_DDR3_USER_PLL_REF_CLK_IO_STD_ENUM unset
PHY_DDR3_USER_RZQ_IO_STD_ENUM unset
PHY_DDR3_AC_IO_STD_ENUM unset
PHY_DDR3_AC_MODE_ENUM unset
PHY_DDR3_AC_SLEW_RATE_ENUM SLEW_RATE_FAST
PHY_DDR3_CK_IO_STD_ENUM unset
PHY_DDR3_CK_MODE_ENUM unset
PHY_DDR3_CK_SLEW_RATE_ENUM SLEW_RATE_FAST
PHY_DDR3_DATA_IO_STD_ENUM unset
PHY_DDR3_DATA_OUT_MODE_ENUM unset
PHY_DDR3_DATA_IN_MODE_ENUM unset
PHY_DDR3_AUTO_STARTING_VREFIN_EN true
PHY_DDR3_STARTING_VREFIN 70.0
PHY_DDR3_PLL_REF_CLK_IO_STD_ENUM unset
PHY_DDR3_RZQ_IO_STD_ENUM unset
PHY_DDR3_CAL_ADDR0 0
PHY_DDR3_CAL_ADDR1 8
PHY_DDR3_CAL_ENABLE_NON_DES false
PHY_DDR4_CONFIG_ENUM CONFIG_PHY_AND_HARD_CTRL
PHY_DDR4_USER_PING_PONG_EN false
PHY_DDR4_MEM_CLK_FREQ_MHZ 1066.667
PHY_DDR4_DEFAULT_REF_CLK_FREQ false
PHY_DDR4_USER_REF_CLK_FREQ_MHZ 133.333
PHY_DDR4_REF_CLK_JITTER_PS 10.0
PHY_DDR4_RATE_ENUM RATE_HALF
PHY_DDR4_CORE_CLKS_SHARING_ENUM CORE_CLKS_SHARING_DISABLED
PHY_DDR4_IO_VOLTAGE 1.2
PHY_DDR4_DEFAULT_IO false
PHY_DDR4_HPS_ENABLE_EARLY_RELEASE true
PHY_DDR4_USER_PERIODIC_OCT_RECAL_ENUM PERIODIC_OCT_RECAL_AUTO
PHY_DDR4_REF_CLK_FREQ_MHZ 133.333
PHY_DDR4_PING_PONG_EN false
PHY_DDR4_USER_AC_IO_STD_ENUM IO_STD_SSTL_12
PHY_DDR4_USER_AC_MODE_ENUM OUT_OCT_40_CAL
PHY_DDR4_USER_AC_SLEW_RATE_ENUM SLEW_RATE_FAST
PHY_DDR4_USER_CK_IO_STD_ENUM IO_STD_SSTL_12
PHY_DDR4_USER_CK_MODE_ENUM OUT_OCT_40_CAL
PHY_DDR4_USER_CK_SLEW_RATE_ENUM SLEW_RATE_FAST
PHY_DDR4_USER_DATA_IO_STD_ENUM IO_STD_POD_12
PHY_DDR4_USER_DATA_OUT_MODE_ENUM OUT_OCT_34_CAL
PHY_DDR4_USER_DATA_IN_MODE_ENUM IN_OCT_60_CAL
PHY_DDR4_USER_AUTO_STARTING_VREFIN_EN true
PHY_DDR4_USER_STARTING_VREFIN 70.0
PHY_DDR4_USER_PLL_REF_CLK_IO_STD_ENUM IO_STD_LVDS
PHY_DDR4_USER_RZQ_IO_STD_ENUM IO_STD_CMOS_12
PHY_DDR4_AC_IO_STD_ENUM IO_STD_SSTL_12
PHY_DDR4_AC_MODE_ENUM OUT_OCT_40_CAL
PHY_DDR4_AC_SLEW_RATE_ENUM SLEW_RATE_FAST
PHY_DDR4_CK_IO_STD_ENUM IO_STD_SSTL_12
PHY_DDR4_CK_MODE_ENUM OUT_OCT_40_CAL
PHY_DDR4_CK_SLEW_RATE_ENUM SLEW_RATE_FAST
PHY_DDR4_DATA_IO_STD_ENUM IO_STD_POD_12
PHY_DDR4_DATA_OUT_MODE_ENUM OUT_OCT_34_CAL
PHY_DDR4_DATA_IN_MODE_ENUM IN_OCT_60_CAL
PHY_DDR4_AUTO_STARTING_VREFIN_EN true
PHY_DDR4_STARTING_VREFIN 68.0
PHY_DDR4_PLL_REF_CLK_IO_STD_ENUM IO_STD_LVDS
PHY_DDR4_RZQ_IO_STD_ENUM IO_STD_CMOS_12
PHY_QDR2_CONFIG_ENUM CONFIG_PHY_AND_SOFT_CTRL
PHY_QDR2_USER_PING_PONG_EN false
PHY_QDR2_MEM_CLK_FREQ_MHZ 633.333
PHY_QDR2_DEFAULT_REF_CLK_FREQ true
PHY_QDR2_USER_REF_CLK_FREQ_MHZ -1.0
PHY_QDR2_REF_CLK_JITTER_PS 10.0
PHY_QDR2_RATE_ENUM RATE_HALF
PHY_QDR2_CORE_CLKS_SHARING_ENUM CORE_CLKS_SHARING_DISABLED
PHY_QDR2_IO_VOLTAGE 1.5
PHY_QDR2_DEFAULT_IO true
PHY_QDR2_HPS_ENABLE_EARLY_RELEASE false
PHY_QDR2_USER_PERIODIC_OCT_RECAL_ENUM PERIODIC_OCT_RECAL_AUTO
PHY_QDR2_REF_CLK_FREQ_MHZ -1.0
PHY_QDR2_PING_PONG_EN false
PHY_QDR2_USER_AC_IO_STD_ENUM unset
PHY_QDR2_USER_AC_MODE_ENUM unset
PHY_QDR2_USER_AC_SLEW_RATE_ENUM SLEW_RATE_FAST
PHY_QDR2_USER_CK_IO_STD_ENUM unset
PHY_QDR2_USER_CK_MODE_ENUM unset
PHY_QDR2_USER_CK_SLEW_RATE_ENUM SLEW_RATE_FAST
PHY_QDR2_USER_DATA_IO_STD_ENUM unset
PHY_QDR2_USER_DATA_OUT_MODE_ENUM unset
PHY_QDR2_USER_DATA_IN_MODE_ENUM unset
PHY_QDR2_USER_AUTO_STARTING_VREFIN_EN true
PHY_QDR2_USER_STARTING_VREFIN 70.0
PHY_QDR2_USER_PLL_REF_CLK_IO_STD_ENUM unset
PHY_QDR2_USER_RZQ_IO_STD_ENUM unset
PHY_QDR2_AC_IO_STD_ENUM unset
PHY_QDR2_AC_MODE_ENUM unset
PHY_QDR2_AC_SLEW_RATE_ENUM SLEW_RATE_FAST
PHY_QDR2_CK_IO_STD_ENUM unset
PHY_QDR2_CK_MODE_ENUM unset
PHY_QDR2_CK_SLEW_RATE_ENUM SLEW_RATE_FAST
PHY_QDR2_DATA_IO_STD_ENUM unset
PHY_QDR2_DATA_OUT_MODE_ENUM unset
PHY_QDR2_DATA_IN_MODE_ENUM unset
PHY_QDR2_AUTO_STARTING_VREFIN_EN true
PHY_QDR2_STARTING_VREFIN 70.0
PHY_QDR2_PLL_REF_CLK_IO_STD_ENUM unset
PHY_QDR2_RZQ_IO_STD_ENUM unset
PHY_QDR4_CONFIG_ENUM CONFIG_PHY_AND_SOFT_CTRL
PHY_QDR4_USER_PING_PONG_EN false
PHY_QDR4_MEM_CLK_FREQ_MHZ 1066.667
PHY_QDR4_DEFAULT_REF_CLK_FREQ true
PHY_QDR4_USER_REF_CLK_FREQ_MHZ -1.0
PHY_QDR4_REF_CLK_JITTER_PS 10.0
PHY_QDR4_RATE_ENUM RATE_QUARTER
PHY_QDR4_CORE_CLKS_SHARING_ENUM CORE_CLKS_SHARING_DISABLED
PHY_QDR4_IO_VOLTAGE 1.2
PHY_QDR4_DEFAULT_IO true
PHY_QDR4_HPS_ENABLE_EARLY_RELEASE false
PHY_QDR4_USER_PERIODIC_OCT_RECAL_ENUM PERIODIC_OCT_RECAL_AUTO
PHY_QDR4_REF_CLK_FREQ_MHZ -1.0
PHY_QDR4_PING_PONG_EN false
PHY_QDR4_USER_AC_IO_STD_ENUM unset
PHY_QDR4_USER_AC_MODE_ENUM unset
PHY_QDR4_USER_AC_SLEW_RATE_ENUM SLEW_RATE_FAST
PHY_QDR4_USER_CK_IO_STD_ENUM unset
PHY_QDR4_USER_CK_MODE_ENUM unset
PHY_QDR4_USER_CK_SLEW_RATE_ENUM SLEW_RATE_FAST
PHY_QDR4_USER_DATA_IO_STD_ENUM unset
PHY_QDR4_USER_DATA_OUT_MODE_ENUM unset
PHY_QDR4_USER_DATA_IN_MODE_ENUM unset
PHY_QDR4_USER_AUTO_STARTING_VREFIN_EN true
PHY_QDR4_USER_STARTING_VREFIN 70.0
PHY_QDR4_USER_PLL_REF_CLK_IO_STD_ENUM unset
PHY_QDR4_USER_RZQ_IO_STD_ENUM unset
PHY_QDR4_AC_IO_STD_ENUM unset
PHY_QDR4_AC_MODE_ENUM unset
PHY_QDR4_AC_SLEW_RATE_ENUM SLEW_RATE_FAST
PHY_QDR4_CK_IO_STD_ENUM unset
PHY_QDR4_CK_MODE_ENUM unset
PHY_QDR4_CK_SLEW_RATE_ENUM SLEW_RATE_FAST
PHY_QDR4_DATA_IO_STD_ENUM unset
PHY_QDR4_DATA_OUT_MODE_ENUM unset
PHY_QDR4_DATA_IN_MODE_ENUM unset
PHY_QDR4_AUTO_STARTING_VREFIN_EN true
PHY_QDR4_STARTING_VREFIN 70.0
PHY_QDR4_PLL_REF_CLK_IO_STD_ENUM unset
PHY_QDR4_RZQ_IO_STD_ENUM unset
PHY_RLD2_CONFIG_ENUM CONFIG_PHY_AND_SOFT_CTRL
PHY_RLD2_USER_PING_PONG_EN false
PHY_RLD2_MEM_CLK_FREQ_MHZ 533.333
PHY_RLD2_DEFAULT_REF_CLK_FREQ true
PHY_RLD2_USER_REF_CLK_FREQ_MHZ -1.0
PHY_RLD2_REF_CLK_JITTER_PS 10.0
PHY_RLD2_RATE_ENUM RATE_HALF
PHY_RLD2_CORE_CLKS_SHARING_ENUM CORE_CLKS_SHARING_DISABLED
PHY_RLD2_IO_VOLTAGE 1.8
PHY_RLD2_DEFAULT_IO true
PHY_RLD2_HPS_ENABLE_EARLY_RELEASE false
PHY_RLD2_USER_PERIODIC_OCT_RECAL_ENUM PERIODIC_OCT_RECAL_AUTO
PHY_RLD2_REF_CLK_FREQ_MHZ -1.0
PHY_RLD2_PING_PONG_EN false
PHY_RLD2_USER_AC_IO_STD_ENUM unset
PHY_RLD2_USER_AC_MODE_ENUM unset
PHY_RLD2_USER_AC_SLEW_RATE_ENUM SLEW_RATE_FAST
PHY_RLD2_USER_CK_IO_STD_ENUM unset
PHY_RLD2_USER_CK_MODE_ENUM unset
PHY_RLD2_USER_CK_SLEW_RATE_ENUM SLEW_RATE_FAST
PHY_RLD2_USER_DATA_IO_STD_ENUM unset
PHY_RLD2_USER_DATA_OUT_MODE_ENUM unset
PHY_RLD2_USER_DATA_IN_MODE_ENUM unset
PHY_RLD2_USER_AUTO_STARTING_VREFIN_EN true
PHY_RLD2_USER_STARTING_VREFIN 70.0
PHY_RLD2_USER_PLL_REF_CLK_IO_STD_ENUM unset
PHY_RLD2_USER_RZQ_IO_STD_ENUM unset
PHY_RLD2_AC_IO_STD_ENUM unset
PHY_RLD2_AC_MODE_ENUM unset
PHY_RLD2_AC_SLEW_RATE_ENUM SLEW_RATE_FAST
PHY_RLD2_CK_IO_STD_ENUM unset
PHY_RLD2_CK_MODE_ENUM unset
PHY_RLD2_CK_SLEW_RATE_ENUM SLEW_RATE_FAST
PHY_RLD2_DATA_IO_STD_ENUM unset
PHY_RLD2_DATA_OUT_MODE_ENUM unset
PHY_RLD2_DATA_IN_MODE_ENUM unset
PHY_RLD2_AUTO_STARTING_VREFIN_EN true
PHY_RLD2_STARTING_VREFIN 70.0
PHY_RLD2_PLL_REF_CLK_IO_STD_ENUM unset
PHY_RLD2_RZQ_IO_STD_ENUM unset
PHY_RLD3_CONFIG_ENUM CONFIG_PHY_ONLY
PHY_RLD3_USER_PING_PONG_EN false
PHY_RLD3_MEM_CLK_FREQ_MHZ 1066.667
PHY_RLD3_DEFAULT_REF_CLK_FREQ true
PHY_RLD3_USER_REF_CLK_FREQ_MHZ -1.0
PHY_RLD3_REF_CLK_JITTER_PS 10.0
PHY_RLD3_RATE_ENUM RATE_QUARTER
PHY_RLD3_CORE_CLKS_SHARING_ENUM CORE_CLKS_SHARING_DISABLED
PHY_RLD3_IO_VOLTAGE 1.2
PHY_RLD3_DEFAULT_IO true
PHY_RLD3_HPS_ENABLE_EARLY_RELEASE false
PHY_RLD3_USER_PERIODIC_OCT_RECAL_ENUM PERIODIC_OCT_RECAL_AUTO
PHY_RLD3_REF_CLK_FREQ_MHZ -1.0
PHY_RLD3_PING_PONG_EN false
PHY_RLD3_USER_AC_IO_STD_ENUM unset
PHY_RLD3_USER_AC_MODE_ENUM unset
PHY_RLD3_USER_AC_SLEW_RATE_ENUM SLEW_RATE_FAST
PHY_RLD3_USER_CK_IO_STD_ENUM unset
PHY_RLD3_USER_CK_MODE_ENUM unset
PHY_RLD3_USER_CK_SLEW_RATE_ENUM SLEW_RATE_FAST
PHY_RLD3_USER_DATA_IO_STD_ENUM unset
PHY_RLD3_USER_DATA_OUT_MODE_ENUM unset
PHY_RLD3_USER_DATA_IN_MODE_ENUM unset
PHY_RLD3_USER_AUTO_STARTING_VREFIN_EN true
PHY_RLD3_USER_STARTING_VREFIN 70.0
PHY_RLD3_USER_PLL_REF_CLK_IO_STD_ENUM unset
PHY_RLD3_USER_RZQ_IO_STD_ENUM unset
PHY_RLD3_AC_IO_STD_ENUM unset
PHY_RLD3_AC_MODE_ENUM unset
PHY_RLD3_AC_SLEW_RATE_ENUM SLEW_RATE_FAST
PHY_RLD3_CK_IO_STD_ENUM unset
PHY_RLD3_CK_MODE_ENUM unset
PHY_RLD3_CK_SLEW_RATE_ENUM SLEW_RATE_FAST
PHY_RLD3_DATA_IO_STD_ENUM unset
PHY_RLD3_DATA_OUT_MODE_ENUM unset
PHY_RLD3_DATA_IN_MODE_ENUM unset
PHY_RLD3_AUTO_STARTING_VREFIN_EN true
PHY_RLD3_STARTING_VREFIN 70.0
PHY_RLD3_PLL_REF_CLK_IO_STD_ENUM unset
PHY_RLD3_RZQ_IO_STD_ENUM unset
PHY_LPDDR3_CONFIG_ENUM CONFIG_PHY_AND_HARD_CTRL
PHY_LPDDR3_USER_PING_PONG_EN false
PHY_LPDDR3_MEM_CLK_FREQ_MHZ 800.0
PHY_LPDDR3_DEFAULT_REF_CLK_FREQ true
PHY_LPDDR3_USER_REF_CLK_FREQ_MHZ -1.0
PHY_LPDDR3_REF_CLK_JITTER_PS 10.0
PHY_LPDDR3_RATE_ENUM RATE_HALF
PHY_LPDDR3_CORE_CLKS_SHARING_ENUM CORE_CLKS_SHARING_DISABLED
PHY_LPDDR3_IO_VOLTAGE 1.2
PHY_LPDDR3_DEFAULT_IO true
PHY_LPDDR3_HPS_ENABLE_EARLY_RELEASE false
PHY_LPDDR3_USER_PERIODIC_OCT_RECAL_ENUM PERIODIC_OCT_RECAL_AUTO
PHY_LPDDR3_REF_CLK_FREQ_MHZ -1.0
PHY_LPDDR3_PING_PONG_EN false
PHY_LPDDR3_USER_AC_IO_STD_ENUM unset
PHY_LPDDR3_USER_AC_MODE_ENUM unset
PHY_LPDDR3_USER_AC_SLEW_RATE_ENUM SLEW_RATE_FAST
PHY_LPDDR3_USER_CK_IO_STD_ENUM unset
PHY_LPDDR3_USER_CK_MODE_ENUM unset
PHY_LPDDR3_USER_CK_SLEW_RATE_ENUM SLEW_RATE_FAST
PHY_LPDDR3_USER_DATA_IO_STD_ENUM unset
PHY_LPDDR3_USER_DATA_OUT_MODE_ENUM unset
PHY_LPDDR3_USER_DATA_IN_MODE_ENUM unset
PHY_LPDDR3_USER_AUTO_STARTING_VREFIN_EN true
PHY_LPDDR3_USER_STARTING_VREFIN 70.0
PHY_LPDDR3_USER_PLL_REF_CLK_IO_STD_ENUM unset
PHY_LPDDR3_USER_RZQ_IO_STD_ENUM unset
PHY_LPDDR3_AC_IO_STD_ENUM unset
PHY_LPDDR3_AC_MODE_ENUM unset
PHY_LPDDR3_AC_SLEW_RATE_ENUM SLEW_RATE_FAST
PHY_LPDDR3_CK_IO_STD_ENUM unset
PHY_LPDDR3_CK_MODE_ENUM unset
PHY_LPDDR3_CK_SLEW_RATE_ENUM SLEW_RATE_FAST
PHY_LPDDR3_DATA_IO_STD_ENUM unset
PHY_LPDDR3_DATA_OUT_MODE_ENUM unset
PHY_LPDDR3_DATA_IN_MODE_ENUM unset
PHY_LPDDR3_AUTO_STARTING_VREFIN_EN true
PHY_LPDDR3_STARTING_VREFIN 70.0
PHY_LPDDR3_PLL_REF_CLK_IO_STD_ENUM unset
PHY_LPDDR3_RZQ_IO_STD_ENUM unset
MEM_FORMAT_ENUM MEM_FORMAT_UDIMM
MEM_READ_LATENCY 16.0
MEM_WRITE_LATENCY 11
MEM_BURST_LENGTH 8
MEM_DATA_MASK_EN true
MEM_HAS_SIM_SUPPORT false
MEM_NUM_OF_PHYSICAL_RANKS 1
MEM_NUM_OF_LOGICAL_RANKS 1
MEM_TTL_DATA_WIDTH 32
MEM_TTL_NUM_OF_READ_GROUPS 4
MEM_TTL_NUM_OF_WRITE_GROUPS 4
MEM_DDR3_FORMAT_ENUM MEM_FORMAT_UDIMM
MEM_DDR3_DQ_WIDTH 32
MEM_DDR3_DQ_PER_DQS 8
MEM_DDR3_DISCRETE_CS_WIDTH 1
MEM_DDR3_NUM_OF_DIMMS 1
MEM_DDR3_RANKS_PER_DIMM 1
MEM_DDR3_CKE_PER_DIMM 1
MEM_DDR3_CK_WIDTH 1
MEM_DDR3_ROW_ADDR_WIDTH 15
MEM_DDR3_COL_ADDR_WIDTH 10
MEM_DDR3_BANK_ADDR_WIDTH 3
MEM_DDR3_DM_EN true
MEM_DDR3_DISCRETE_MIRROR_ADDRESSING_EN false
MEM_DDR3_MIRROR_ADDRESSING_EN true
MEM_DDR3_HIDE_ADV_MR_SETTINGS true
MEM_DDR3_RDIMM_CONFIG 0000000000000000
MEM_DDR3_LRDIMM_EXTENDED_CONFIG 000000000000000000
MEM_DDR3_ALERT_N_PLACEMENT_ENUM DDR3_ALERT_N_PLACEMENT_AC_LANES
MEM_DDR3_ALERT_N_DQS_GROUP 0
MEM_DDR3_DQS_WIDTH 8
MEM_DDR3_DM_WIDTH 1
MEM_DDR3_CS_WIDTH 1
MEM_DDR3_CS_PER_DIMM 1
MEM_DDR3_CKE_WIDTH 1
MEM_DDR3_ODT_WIDTH 1
MEM_DDR3_ADDR_WIDTH 1
MEM_DDR3_RM_WIDTH 0
MEM_DDR3_AC_PAR_EN false
MEM_DDR3_NUM_OF_PHYSICAL_RANKS 1
MEM_DDR3_NUM_OF_LOGICAL_RANKS 1
MEM_DDR3_TTL_DQS_WIDTH 8
MEM_DDR3_TTL_DQ_WIDTH 72
MEM_DDR3_TTL_DM_WIDTH 1
MEM_DDR3_TTL_CS_WIDTH 1
MEM_DDR3_TTL_CK_WIDTH 1
MEM_DDR3_TTL_CKE_WIDTH 1
MEM_DDR3_TTL_ODT_WIDTH 1
MEM_DDR3_TTL_BANK_ADDR_WIDTH 3
MEM_DDR3_TTL_ADDR_WIDTH 1
MEM_DDR3_TTL_RM_WIDTH 0
MEM_DDR3_TTL_NUM_OF_DIMMS 1
MEM_DDR3_TTL_NUM_OF_PHYSICAL_RANKS 1
MEM_DDR3_TTL_NUM_OF_LOGICAL_RANKS 1
MEM_DDR3_MR0 0
MEM_DDR3_MR1 0
MEM_DDR3_MR2 0
MEM_DDR3_MR3 0
MEM_DDR3_ADDRESS_MIRROR_BITVEC 0
MEM_DDR3_BL_ENUM DDR3_BL_BL8
MEM_DDR3_BT_ENUM DDR3_BT_SEQUENTIAL
MEM_DDR3_ASR_ENUM DDR3_ASR_MANUAL
MEM_DDR3_SRT_ENUM DDR3_SRT_NORMAL
MEM_DDR3_PD_ENUM DDR3_PD_OFF
MEM_DDR3_DRV_STR_ENUM DDR3_DRV_STR_RZQ_7
MEM_DDR3_DLL_EN true
MEM_DDR3_RTT_NOM_ENUM DDR3_RTT_NOM_ODT_DISABLED
MEM_DDR3_RTT_WR_ENUM DDR3_RTT_WR_RZQ_4
MEM_DDR3_WTCL 10
MEM_DDR3_ATCL_ENUM DDR3_ATCL_DISABLED
MEM_DDR3_TCL 14
MEM_DDR3_USE_DEFAULT_ODT true
MEM_DDR3_R_ODTN_1X1 Rank 0
MEM_DDR3_R_ODT0_1X1 off
MEM_DDR3_W_ODTN_1X1 Rank 0
MEM_DDR3_W_ODT0_1X1 on
MEM_DDR3_R_ODTN_2X2 Rank 0,Rank 1
MEM_DDR3_R_ODT0_2X2 off,off
MEM_DDR3_R_ODT1_2X2 off,off
MEM_DDR3_W_ODTN_2X2 Rank 0,Rank 1
MEM_DDR3_W_ODT0_2X2 on,off
MEM_DDR3_W_ODT1_2X2 off,on
MEM_DDR3_R_ODTN_4X2 Rank 0,Rank 1,Rank 2,Rank 3
MEM_DDR3_R_ODT0_4X2 off,off,on,on
MEM_DDR3_R_ODT1_4X2 on,on,off,off
MEM_DDR3_W_ODTN_4X2 Rank 0,Rank 1,Rank 2,Rank 3
MEM_DDR3_W_ODT0_4X2 off,off,on,on
MEM_DDR3_W_ODT1_4X2 on,on,off,off
MEM_DDR3_R_ODTN_4X4 Rank 0,Rank 1,Rank 2,Rank 3
MEM_DDR3_R_ODT0_4X4 off,off,off,off
MEM_DDR3_R_ODT1_4X4 off,off,on,on
MEM_DDR3_R_ODT2_4X4 off,off,off,off
MEM_DDR3_R_ODT3_4X4 on,on,off,off
MEM_DDR3_W_ODTN_4X4 Rank 0,Rank 1,Rank 2,Rank 3
MEM_DDR3_W_ODT0_4X4 on,on,off,off
MEM_DDR3_W_ODT1_4X4 off,off,on,on
MEM_DDR3_W_ODT2_4X4 off,off,on,on
MEM_DDR3_W_ODT3_4X4 on,on,off,off
MEM_DDR3_R_DERIVED_ODTN ,,
MEM_DDR3_R_DERIVED_ODT0 ,,
MEM_DDR3_R_DERIVED_ODT1 ,,
MEM_DDR3_R_DERIVED_ODT2 ,,
MEM_DDR3_R_DERIVED_ODT3 ,,
MEM_DDR3_W_DERIVED_ODTN ,,
MEM_DDR3_W_DERIVED_ODT0 ,,
MEM_DDR3_W_DERIVED_ODT1 ,,
MEM_DDR3_W_DERIVED_ODT2 ,,
MEM_DDR3_W_DERIVED_ODT3 ,,
MEM_DDR3_SEQ_ODT_TABLE_LO 0
MEM_DDR3_SEQ_ODT_TABLE_HI 0
MEM_DDR3_CTRL_CFG_READ_ODT_CHIP 0
MEM_DDR3_CTRL_CFG_WRITE_ODT_CHIP 0
MEM_DDR3_CTRL_CFG_READ_ODT_RANK 0
MEM_DDR3_CTRL_CFG_WRITE_ODT_RANK 0
MEM_DDR3_SPEEDBIN_ENUM DDR3_SPEEDBIN_2133
MEM_DDR3_TIS_PS 60
MEM_DDR3_TIS_AC_MV 135
MEM_DDR3_TIH_PS 95
MEM_DDR3_TIH_DC_MV 100
MEM_DDR3_TDS_PS 53
MEM_DDR3_TDS_AC_MV 135
MEM_DDR3_TDH_PS 55
MEM_DDR3_TDH_DC_MV 100
MEM_DDR3_TDQSQ_PS 75
MEM_DDR3_TQH_CYC 0.38
MEM_DDR3_TDQSCK_PS 180
MEM_DDR3_TDQSS_CYC 0.27
MEM_DDR3_TQSH_CYC 0.4
MEM_DDR3_TDSH_CYC 0.18
MEM_DDR3_TWLS_PS 125.0
MEM_DDR3_TWLH_PS 125.0
MEM_DDR3_TDSS_CYC 0.18
MEM_DDR3_TINIT_US 500
MEM_DDR3_TMRD_CK_CYC 4
MEM_DDR3_TRAS_NS 33.0
MEM_DDR3_TRCD_NS 13.09
MEM_DDR3_TRP_NS 13.09
MEM_DDR3_TREFI_US 7.8
MEM_DDR3_TRFC_NS 160.0
MEM_DDR3_TWR_NS 15.0
MEM_DDR3_TWTR_CYC 8
MEM_DDR3_TFAW_NS 25.0
MEM_DDR3_TRRD_CYC 6
MEM_DDR3_TRTP_CYC 8
MEM_DDR3_TINIT_CK 499
MEM_DDR3_TDQSCK_DERV_PS 2
MEM_DDR3_TDQSCKDS 450
MEM_DDR3_TDQSCKDM 900
MEM_DDR3_TDQSCKDL 1200
MEM_DDR3_TRAS_CYC 36
MEM_DDR3_TRCD_CYC 14
MEM_DDR3_TRP_CYC 14
MEM_DDR3_TRFC_CYC 171
MEM_DDR3_TWR_CYC 16
MEM_DDR3_TFAW_CYC 27
MEM_DDR3_TREFI_CYC 8320
MEM_DDR3_CFG_GEN_SBE false
MEM_DDR3_CFG_GEN_DBE false
MEM_DDR4_FORMAT_ENUM MEM_FORMAT_UDIMM
MEM_DDR4_DQ_WIDTH 32
MEM_DDR4_DQ_PER_DQS 8
MEM_DDR4_DISCRETE_CS_WIDTH 1
MEM_DDR4_NUM_OF_DIMMS 1
MEM_DDR4_CHIP_ID_WIDTH 0
MEM_DDR4_RANKS_PER_DIMM 1
MEM_DDR4_CKE_PER_DIMM 1
MEM_DDR4_CK_WIDTH 1
MEM_DDR4_ROW_ADDR_WIDTH 15
MEM_DDR4_COL_ADDR_WIDTH 10
MEM_DDR4_BANK_ADDR_WIDTH 2
MEM_DDR4_BANK_GROUP_WIDTH 1
MEM_DDR4_DM_EN true
MEM_DDR4_ALERT_PAR_EN true
MEM_DDR4_ALERT_N_PLACEMENT_ENUM DDR4_ALERT_N_PLACEMENT_DATA_LANES
MEM_DDR4_ALERT_N_DQS_GROUP 3
MEM_DDR4_ALERT_N_AC_LANE 0
MEM_DDR4_ALERT_N_AC_PIN 0
MEM_DDR4_DISCRETE_MIRROR_ADDRESSING_EN false
MEM_DDR4_MIRROR_ADDRESSING_EN true
MEM_DDR4_HIDE_ADV_MR_SETTINGS true
MEM_DDR4_BL_ENUM DDR4_BL_BL8
MEM_DDR4_BT_ENUM DDR4_BT_SEQUENTIAL
MEM_DDR4_TCL 16
MEM_DDR4_RTT_NOM_ENUM DDR4_RTT_NOM_RZQ_6
MEM_DDR4_DLL_EN true
MEM_DDR4_ATCL_ENUM DDR4_ATCL_DISABLED
MEM_DDR4_DRV_STR_ENUM DDR4_DRV_STR_RZQ_7
MEM_DDR4_ASR_ENUM DDR4_ASR_MANUAL_NORMAL
MEM_DDR4_RTT_WR_ENUM DDR4_RTT_WR_ODT_DISABLED
MEM_DDR4_WTCL 11
MEM_DDR4_WRITE_CRC false
MEM_DDR4_GEARDOWN DDR4_GEARDOWN_HR
MEM_DDR4_PER_DRAM_ADDR false
MEM_DDR4_TEMP_SENSOR_READOUT false
MEM_DDR4_FINE_GRANULARITY_REFRESH DDR4_FINE_REFRESH_FIXED_1X
MEM_DDR4_MPR_READ_FORMAT DDR4_MPR_READ_FORMAT_SERIAL
MEM_DDR4_MAX_POWERDOWN false
MEM_DDR4_TEMP_CONTROLLED_RFSH_RANGE DDR4_TEMP_CONTROLLED_RFSH_NORMAL
MEM_DDR4_TEMP_CONTROLLED_RFSH_ENA false
MEM_DDR4_INTERNAL_VREFDQ_MONITOR false
MEM_DDR4_CAL_MODE 0
MEM_DDR4_SELF_RFSH_ABORT false
MEM_DDR4_READ_PREAMBLE_TRAINING false
MEM_DDR4_READ_PREAMBLE 2
MEM_DDR4_WRITE_PREAMBLE 1
MEM_DDR4_AC_PARITY_LATENCY DDR4_AC_PARITY_LATENCY_DISABLE
MEM_DDR4_ODT_IN_POWERDOWN true
MEM_DDR4_RTT_PARK DDR4_RTT_PARK_ODT_DISABLED
MEM_DDR4_AC_PERSISTENT_ERROR false
MEM_DDR4_WRITE_DBI false
MEM_DDR4_READ_DBI true
MEM_DDR4_DEFAULT_VREFOUT true
MEM_DDR4_USER_VREFDQ_TRAINING_VALUE 56.0
MEM_DDR4_USER_VREFDQ_TRAINING_RANGE DDR4_VREFDQ_TRAINING_RANGE_1
MEM_DDR4_RCD_CA_IBT_ENUM DDR4_RCD_CA_IBT_100
MEM_DDR4_RCD_CS_IBT_ENUM DDR4_RCD_CS_IBT_100
MEM_DDR4_RCD_CKE_IBT_ENUM DDR4_RCD_CKE_IBT_100
MEM_DDR4_RCD_ODT_IBT_ENUM DDR4_RCD_ODT_IBT_100
MEM_DDR4_DB_RTT_NOM_ENUM DDR4_DB_RTT_NOM_ODT_DISABLED
MEM_DDR4_DB_RTT_WR_ENUM DDR4_DB_RTT_WR_RZQ_3
MEM_DDR4_DB_RTT_PARK_ENUM DDR4_DB_RTT_PARK_ODT_DISABLED
MEM_DDR4_DB_DQ_DRV_ENUM DDR4_DB_DRV_STR_RZQ_7
MEM_DDR4_SPD_137_RCD_CA_DRV 101
MEM_DDR4_SPD_138_RCD_CK_DRV 5
MEM_DDR4_SPD_140_DRAM_VREFDQ_R0 29
MEM_DDR4_SPD_141_DRAM_VREFDQ_R1 29
MEM_DDR4_SPD_142_DRAM_VREFDQ_R2 29
MEM_DDR4_SPD_143_DRAM_VREFDQ_R3 29
MEM_DDR4_SPD_144_DB_VREFDQ 37
MEM_DDR4_SPD_145_DB_MDQ_DRV 21
MEM_DDR4_SPD_148_DRAM_DRV 0
MEM_DDR4_SPD_149_DRAM_RTT_WR_NOM 20
MEM_DDR4_SPD_152_DRAM_RTT_PARK 39
MEM_DDR4_SPD_133_RCD_DB_VENDOR_LSB 0
MEM_DDR4_SPD_134_RCD_DB_VENDOR_MSB 0
MEM_DDR4_SPD_135_RCD_REV 0
MEM_DDR4_SPD_139_DB_REV 0
MEM_DDR4_LRDIMM_ODT_LESS_BS true
MEM_DDR4_LRDIMM_ODT_LESS_BS_PARK_OHM 240
MEM_DDR4_DQS_WIDTH 4
MEM_DDR4_CS_WIDTH 1
MEM_DDR4_CS_PER_DIMM 1
MEM_DDR4_CKE_WIDTH 1
MEM_DDR4_ODT_WIDTH 1
MEM_DDR4_ADDR_WIDTH 17
MEM_DDR4_RM_WIDTH 0
MEM_DDR4_NUM_OF_PHYSICAL_RANKS 1
MEM_DDR4_NUM_OF_LOGICAL_RANKS 1
MEM_DDR4_VREFDQ_TRAINING_VALUE 72.9
MEM_DDR4_VREFDQ_TRAINING_RANGE DDR4_VREFDQ_TRAINING_RANGE_1
MEM_DDR4_VREFDQ_TRAINING_RANGE_DISP Range 2 - 45% to 77.5%
MEM_DDR4_TTL_DQS_WIDTH 4
MEM_DDR4_TTL_DQ_WIDTH 32
MEM_DDR4_TTL_CS_WIDTH 1
MEM_DDR4_TTL_CK_WIDTH 1
MEM_DDR4_TTL_CKE_WIDTH 1
MEM_DDR4_TTL_ODT_WIDTH 1
MEM_DDR4_TTL_BANK_ADDR_WIDTH 2
MEM_DDR4_TTL_BANK_GROUP_WIDTH 1
MEM_DDR4_TTL_CHIP_ID_WIDTH 0
MEM_DDR4_TTL_ADDR_WIDTH 17
MEM_DDR4_TTL_RM_WIDTH 0
MEM_DDR4_TTL_NUM_OF_DIMMS 1
MEM_DDR4_TTL_NUM_OF_PHYSICAL_RANKS 1
MEM_DDR4_TTL_NUM_OF_LOGICAL_RANKS 1
MEM_DDR4_MR0 2100
MEM_DDR4_MR1 66305
MEM_DDR4_MR2 131088
MEM_DDR4_MR3 197632
MEM_DDR4_MR4 264192
MEM_DDR4_MR5 332832
MEM_DDR4_MR6 395370
MEM_DDR4_RDIMM_CONFIG
MEM_DDR4_LRDIMM_EXTENDED_CONFIG
MEM_DDR4_ADDRESS_MIRROR_BITVEC 0
MEM_DDR4_RCD_PARITY_CONTROL_WORD 13
MEM_DDR4_RCD_COMMAND_LATENCY 1
MEM_DDR4_USE_DEFAULT_ODT true
MEM_DDR4_R_ODTN_1X1 Rank 0
MEM_DDR4_R_ODT0_1X1 off
MEM_DDR4_W_ODTN_1X1 Rank 0
MEM_DDR4_W_ODT0_1X1 on
MEM_DDR4_R_ODTN_2X2 Rank 0,Rank 1
MEM_DDR4_R_ODT0_2X2 off,off
MEM_DDR4_R_ODT1_2X2 off,off
MEM_DDR4_W_ODTN_2X2 Rank 0,Rank 1
MEM_DDR4_W_ODT0_2X2 on,off
MEM_DDR4_W_ODT1_2X2 off,on
MEM_DDR4_R_ODTN_4X2 Rank 0,Rank 1,Rank 2,Rank 3
MEM_DDR4_R_ODT0_4X2 off,off,on,on
MEM_DDR4_R_ODT1_4X2 on,on,off,off
MEM_DDR4_W_ODTN_4X2 Rank 0,Rank 1,Rank 2,Rank 3
MEM_DDR4_W_ODT0_4X2 off,off,on,on
MEM_DDR4_W_ODT1_4X2 on,on,off,off
MEM_DDR4_R_ODTN_4X4 Rank 0,Rank 1,Rank 2,Rank 3
MEM_DDR4_R_ODT0_4X4 off,off,off,off
MEM_DDR4_R_ODT1_4X4 off,off,on,on
MEM_DDR4_R_ODT2_4X4 off,off,off,off
MEM_DDR4_R_ODT3_4X4 on,on,off,off
MEM_DDR4_W_ODTN_4X4 Rank 0,Rank 1,Rank 2,Rank 3
MEM_DDR4_W_ODT0_4X4 on,on,off,off
MEM_DDR4_W_ODT1_4X4 off,off,on,on
MEM_DDR4_W_ODT2_4X4 off,off,on,on
MEM_DDR4_W_ODT3_4X4 on,on,off,off
MEM_DDR4_R_DERIVED_ODTN Rank 0,-,-,-
MEM_DDR4_R_DERIVED_ODT0 (Drive) RZQ/7 (34 Ohm),-,-,-
MEM_DDR4_R_DERIVED_ODT1 -,-,-,-
MEM_DDR4_R_DERIVED_ODT2 -,-,-,-
MEM_DDR4_R_DERIVED_ODT3 -,-,-,-
MEM_DDR4_W_DERIVED_ODTN Rank 0,-,-,-
MEM_DDR4_W_DERIVED_ODT0 (Nominal) RZQ/6 (40 Ohm),-,-,-
MEM_DDR4_W_DERIVED_ODT1 -,-,-,-
MEM_DDR4_W_DERIVED_ODT2 -,-,-,-
MEM_DDR4_W_DERIVED_ODT3 -,-,-,-
MEM_DDR4_SEQ_ODT_TABLE_LO 4
MEM_DDR4_SEQ_ODT_TABLE_HI 0
MEM_DDR4_CTRL_CFG_READ_ODT_CHIP 0
MEM_DDR4_CTRL_CFG_WRITE_ODT_CHIP 1
MEM_DDR4_CTRL_CFG_READ_ODT_RANK 0
MEM_DDR4_CTRL_CFG_WRITE_ODT_RANK 1
MEM_DDR4_SPEEDBIN_ENUM DDR4_SPEEDBIN_2666
MEM_DDR4_TIS_PS 50
MEM_DDR4_TIS_AC_MV 100
MEM_DDR4_TIH_PS 75
MEM_DDR4_TIH_DC_MV 75
MEM_DDR4_TDIVW_TOTAL_UI 0.23
MEM_DDR4_VDIVW_TOTAL 110
MEM_DDR4_TDQSQ_UI 0.19
MEM_DDR4_TQH_UI 0.71
MEM_DDR4_TDVWP_UI 0.72
MEM_DDR4_TDQSCK_PS 160
MEM_DDR4_TDQSS_CYC 0.27
MEM_DDR4_TQSH_CYC 0.46
MEM_DDR4_TDSH_CYC 0.18
MEM_DDR4_TDSS_CYC 0.18
MEM_DDR4_TWLS_PS 122.0
MEM_DDR4_TWLH_PS 122.0
MEM_DDR4_TINIT_US 500
MEM_DDR4_TMRD_CK_CYC 10
MEM_DDR4_TRAS_NS 32.0
MEM_DDR4_TRCD_NS 12.5
MEM_DDR4_TRP_NS 12.5
MEM_DDR4_TREFI_US 7.8
MEM_DDR4_TRFC_NS 260.0
MEM_DDR4_TWR_NS 15.0
MEM_DDR4_TWTR_L_CYC 8
MEM_DDR4_TWTR_S_CYC 3
MEM_DDR4_TFAW_NS 30.0
MEM_DDR4_TRRD_L_CYC 7
MEM_DDR4_TRRD_S_CYC 6
MEM_DDR4_TCCD_L_CYC 6
MEM_DDR4_TCCD_S_CYC 4
MEM_DDR4_TRFC_DLR_NS 90.0
MEM_DDR4_TFAW_DLR_CYC 16
MEM_DDR4_TRRD_DLR_CYC 4
MEM_DDR4_TDIVW_DJ_CYC 0.1
MEM_DDR4_TDQSQ_PS 66
MEM_DDR4_TQH_CYC 0.38
MEM_DDR4_TINIT_CK 533334
MEM_DDR4_TDQSCK_DERV_PS 2
MEM_DDR4_TDQSCKDS 450
MEM_DDR4_TDQSCKDM 900
MEM_DDR4_TDQSCKDL 1200
MEM_DDR4_TRAS_CYC 35
MEM_DDR4_TRCD_CYC 14
MEM_DDR4_TRP_CYC 14
MEM_DDR4_TRFC_CYC 278
MEM_DDR4_TWR_CYC 18
MEM_DDR4_TRTP_CYC 9
MEM_DDR4_TFAW_CYC 32
MEM_DDR4_TREFI_CYC 8320
MEM_DDR4_WRITE_CMD_LATENCY 6
MEM_DDR4_TRFC_DLR_CYC 96
MEM_DDR4_CFG_GEN_SBE false
MEM_DDR4_CFG_GEN_DBE false
MEM_DDR4_LRDIMM_VREFDQ_VALUE
MEM_QDR2_WIDTH_EXPANDED false
MEM_QDR2_DATA_PER_DEVICE 36
MEM_QDR2_ADDR_WIDTH 19
MEM_QDR2_BWS_EN true
MEM_QDR2_BL 4
MEM_QDR2_FORMAT_ENUM MEM_FORMAT_DISCRETE
MEM_QDR2_DEVICE_WIDTH 1
MEM_QDR2_DATA_WIDTH 36
MEM_QDR2_BWS_N_WIDTH 4
MEM_QDR2_BWS_N_PER_DEVICE 4
MEM_QDR2_CQ_WIDTH 1
MEM_QDR2_K_WIDTH 1
MEM_QDR2_TWL_CYC 1
MEM_QDR2_SPEEDBIN_ENUM QDR2_SPEEDBIN_633
MEM_QDR2_TRL_CYC 2.5
MEM_QDR2_TSA_NS 0.23
MEM_QDR2_THA_NS 0.18
MEM_QDR2_TSD_NS 0.23
MEM_QDR2_THD_NS 0.18
MEM_QDR2_TCQD_NS 0.09
MEM_QDR2_TCQDOH_NS -0.09
MEM_QDR2_INTERNAL_JITTER_NS 0.08
MEM_QDR2_TCQH_NS 0.71
MEM_QDR2_TCCQO_NS 0.45
MEM_QDR4_WIDTH_EXPANDED false
MEM_QDR4_DQ_PER_PORT_PER_DEVICE 36
MEM_QDR4_ADDR_WIDTH 21
MEM_QDR4_CK_ODT_MODE_ENUM QDR4_ODT_25_PCT
MEM_QDR4_AC_ODT_MODE_ENUM QDR4_ODT_25_PCT
MEM_QDR4_DATA_ODT_MODE_ENUM QDR4_ODT_25_PCT
MEM_QDR4_PU_OUTPUT_DRIVE_MODE_ENUM QDR4_OUTPUT_DRIVE_25_PCT
MEM_QDR4_PD_OUTPUT_DRIVE_MODE_ENUM QDR4_OUTPUT_DRIVE_25_PCT
MEM_QDR4_DATA_INV_ENA true
MEM_QDR4_ADDR_INV_ENA false
MEM_QDR4_FORMAT_ENUM MEM_FORMAT_DISCRETE
MEM_QDR4_DEVICE_WIDTH 1
MEM_QDR4_DEVICE_DEPTH 1
MEM_QDR4_DQ_PER_RD_GROUP 18
MEM_QDR4_DQ_PER_WR_GROUP 18
MEM_QDR4_DQ_WIDTH 72
MEM_QDR4_QK_WIDTH 4
MEM_QDR4_DK_WIDTH 4
MEM_QDR4_DINV_WIDTH 4
MEM_QDR4_USE_ADDR_PARITY false
MEM_QDR4_DQ_PER_PORT_WIDTH 36
MEM_QDR4_QK_PER_PORT_WIDTH 2
MEM_QDR4_DK_PER_PORT_WIDTH 2
MEM_QDR4_DINV_PER_PORT_WIDTH 2
MEM_QDR4_BL 2
MEM_QDR4_TRL_CYC 8
MEM_QDR4_TWL_CYC 5
MEM_QDR4_CR0 0
MEM_QDR4_CR1 0
MEM_QDR4_CR2 0
MEM_QDR4_SPEEDBIN_ENUM QDR4_SPEEDBIN_2133
MEM_QDR4_TISH_PS 150
MEM_QDR4_TQKQ_MAX_PS 75
MEM_QDR4_TQH_CYC 0.4
MEM_QDR4_TCKDK_MAX_PS 150
MEM_QDR4_TCKDK_MIN_PS -150
MEM_QDR4_TCKQK_MAX_PS 225
MEM_QDR4_TASH_PS 170
MEM_QDR4_TCSH_PS 170
MEM_RLD2_WIDTH_EXPANDED false
MEM_RLD2_DQ_PER_DEVICE 9
MEM_RLD2_ADDR_WIDTH 21
MEM_RLD2_BANK_ADDR_WIDTH 3
MEM_RLD2_DM_EN true
MEM_RLD2_BL 4
MEM_RLD2_CONFIG_ENUM RLD2_CONFIG_TRC_8_TRL_8_TWL_9
MEM_RLD2_DRIVE_IMPEDENCE_ENUM RLD2_DRIVE_IMPEDENCE_INTERNAL_50
MEM_RLD2_ODT_MODE_ENUM RLD2_ODT_ON
MEM_RLD2_FORMAT_ENUM MEM_FORMAT_DISCRETE
MEM_RLD2_DEVICE_WIDTH 1
MEM_RLD2_DEVICE_DEPTH 1
MEM_RLD2_DQ_WIDTH 9
MEM_RLD2_DQ_PER_RD_GROUP 9
MEM_RLD2_DQ_PER_WR_GROUP 9
MEM_RLD2_QK_WIDTH 1
MEM_RLD2_DK_WIDTH 1
MEM_RLD2_DM_WIDTH 1
MEM_RLD2_CS_WIDTH 1
MEM_RLD2_TRC 8
MEM_RLD2_TRL 8
MEM_RLD2_TWL 9
MEM_RLD2_MR 0
MEM_RLD2_SPEEDBIN_ENUM RLD2_SPEEDBIN_18
MEM_RLD2_REFRESH_INTERVAL_US 0.24
MEM_RLD2_TCKH_CYC 0.45
MEM_RLD2_TQKH_HCYC 0.9
MEM_RLD2_TAS_NS 0.3
MEM_RLD2_TAH_NS 0.3
MEM_RLD2_TDS_NS 0.17
MEM_RLD2_TDH_NS 0.17
MEM_RLD2_TQKQ_MAX_NS 0.12
MEM_RLD2_TQKQ_MIN_NS -0.12
MEM_RLD2_TCKDK_MAX_NS 0.3
MEM_RLD2_TCKDK_MIN_NS -0.3
MEM_RLD2_TCKQK_MAX_NS 0.2
MEM_RLD3_WIDTH_EXPANDED false
MEM_RLD3_DEPTH_EXPANDED false
MEM_RLD3_DQ_PER_DEVICE 36
MEM_RLD3_ADDR_WIDTH 20
MEM_RLD3_BANK_ADDR_WIDTH 4
MEM_RLD3_DM_EN true
MEM_RLD3_BL 2
MEM_RLD3_DATA_LATENCY_MODE_ENUM RLD3_DL_RL16_WL17
MEM_RLD3_T_RC_MODE_ENUM RLD3_TRC_9
MEM_RLD3_OUTPUT_DRIVE_MODE_ENUM RLD3_OUTPUT_DRIVE_40
MEM_RLD3_ODT_MODE_ENUM RLD3_ODT_40
MEM_RLD3_AREF_PROTOCOL_ENUM RLD3_AREF_BAC
MEM_RLD3_WRITE_PROTOCOL_ENUM RLD3_WRITE_1BANK
MEM_RLD3_FORMAT_ENUM MEM_FORMAT_DISCRETE
MEM_RLD3_DEVICE_WIDTH 1
MEM_RLD3_DEVICE_DEPTH 1
MEM_RLD3_DQ_WIDTH 36
MEM_RLD3_DQ_PER_RD_GROUP 9
MEM_RLD3_DQ_PER_WR_GROUP 18
MEM_RLD3_QK_WIDTH 4
MEM_RLD3_DK_WIDTH 2
MEM_RLD3_DM_WIDTH 2
MEM_RLD3_CS_WIDTH 1
MEM_RLD3_MR0 0
MEM_RLD3_MR1 0
MEM_RLD3_MR2 0
MEM_RLD3_SPEEDBIN_ENUM RLD3_SPEEDBIN_093E
MEM_RLD3_TDS_PS -30
MEM_RLD3_TDS_AC_MV 150
MEM_RLD3_TDH_PS 5
MEM_RLD3_TDH_DC_MV 100
MEM_RLD3_TQKQ_MAX_PS 75
MEM_RLD3_TQH_CYC 0.38
MEM_RLD3_TCKDK_MAX_CYC 0.27
MEM_RLD3_TCKDK_MIN_CYC -0.27
MEM_RLD3_TCKQK_MAX_PS 135
MEM_RLD3_TIS_PS 85
MEM_RLD3_TIS_AC_MV 150
MEM_RLD3_TIH_PS 65
MEM_RLD3_TIH_DC_MV 100
MEM_LPDDR3_DQ_WIDTH 32
MEM_LPDDR3_DISCRETE_CS_WIDTH 1
MEM_LPDDR3_CK_WIDTH 1
MEM_LPDDR3_DM_EN true
MEM_LPDDR3_ROW_ADDR_WIDTH 15
MEM_LPDDR3_COL_ADDR_WIDTH 10
MEM_LPDDR3_BANK_ADDR_WIDTH 3
MEM_LPDDR3_DQS_WIDTH 1
MEM_LPDDR3_DM_WIDTH 1
MEM_LPDDR3_CS_WIDTH 1
MEM_LPDDR3_CKE_WIDTH 1
MEM_LPDDR3_ODT_WIDTH 1
MEM_LPDDR3_ADDR_WIDTH 10
MEM_LPDDR3_DQ_PER_DQS 8
MEM_LPDDR3_FORMAT_ENUM MEM_FORMAT_DISCRETE
MEM_LPDDR3_MR1 0
MEM_LPDDR3_MR2 0
MEM_LPDDR3_MR3 0
MEM_LPDDR3_MR11 0
MEM_LPDDR3_BL LPDDR3_BL_BL8
MEM_LPDDR3_DATA_LATENCY LPDDR3_DL_RL12_WL6
MEM_LPDDR3_DRV_STR LPDDR3_DRV_STR_40D_40U
MEM_LPDDR3_DQODT LPDDR3_DQODT_DISABLE
MEM_LPDDR3_PDODT LPDDR3_PDODT_DISABLED
MEM_LPDDR3_WLSELECT Set A
MEM_LPDDR3_NWR LPDDR3_NWR_NWR12
MEM_LPDDR3_NUM_OF_LOGICAL_RANKS 1
MEM_LPDDR3_NUM_OF_PHYSICAL_RANKS 1
MEM_LPDDR3_USE_DEFAULT_ODT true
MEM_LPDDR3_R_ODTN_1X1 Rank 0
MEM_LPDDR3_R_ODT0_1X1 off
MEM_LPDDR3_W_ODTN_1X1 Rank 0
MEM_LPDDR3_W_ODT0_1X1 on
MEM_LPDDR3_R_ODTN_2X2 Rank 0,Rank 1
MEM_LPDDR3_R_ODT0_2X2 off,off
MEM_LPDDR3_R_ODT1_2X2 off,off
MEM_LPDDR3_W_ODTN_2X2 Rank 0,Rank 1
MEM_LPDDR3_W_ODT0_2X2 on,on
MEM_LPDDR3_W_ODT1_2X2 off,off
MEM_LPDDR3_R_ODTN_4X4 Rank 0,Rank 1,Rank 2,Rank 3
MEM_LPDDR3_R_ODT0_4X4 off,off,off,off
MEM_LPDDR3_R_ODT1_4X4 off,off,off,off
MEM_LPDDR3_R_ODT2_4X4 off,off,off,off
MEM_LPDDR3_R_ODT3_4X4 off,off,off,off
MEM_LPDDR3_W_ODTN_4X4 Rank 0,Rank 1,Rank 2,Rank 3
MEM_LPDDR3_W_ODT0_4X4 on,on,on,on
MEM_LPDDR3_W_ODT1_4X4 off,off,off,off
MEM_LPDDR3_W_ODT2_4X4 off,off,off,off
MEM_LPDDR3_W_ODT3_4X4 off,off,off,off
MEM_LPDDR3_R_DERIVED_ODTN ,,
MEM_LPDDR3_R_DERIVED_ODT0 ,,
MEM_LPDDR3_R_DERIVED_ODT1 ,,
MEM_LPDDR3_R_DERIVED_ODT2 ,,
MEM_LPDDR3_R_DERIVED_ODT3 ,,
MEM_LPDDR3_W_DERIVED_ODTN ,,
MEM_LPDDR3_W_DERIVED_ODT0 ,,
MEM_LPDDR3_W_DERIVED_ODT1 ,,
MEM_LPDDR3_W_DERIVED_ODT2 ,,
MEM_LPDDR3_W_DERIVED_ODT3 ,,
MEM_LPDDR3_SEQ_ODT_TABLE_LO 0
MEM_LPDDR3_SEQ_ODT_TABLE_HI 0
MEM_LPDDR3_CTRL_CFG_READ_ODT_CHIP 0
MEM_LPDDR3_CTRL_CFG_WRITE_ODT_CHIP 0
MEM_LPDDR3_CTRL_CFG_READ_ODT_RANK 0
MEM_LPDDR3_CTRL_CFG_WRITE_ODT_RANK 0
MEM_LPDDR3_SPEEDBIN_ENUM LPDDR3_SPEEDBIN_1600
MEM_LPDDR3_TIS_PS 75
MEM_LPDDR3_TIS_AC_MV 150
MEM_LPDDR3_TIH_PS 100
MEM_LPDDR3_TIH_DC_MV 100
MEM_LPDDR3_TDS_PS 75
MEM_LPDDR3_TDS_AC_MV 150
MEM_LPDDR3_TDH_PS 100
MEM_LPDDR3_TDH_DC_MV 100
MEM_LPDDR3_TDQSQ_PS 135
MEM_LPDDR3_TQH_CYC 0.38
MEM_LPDDR3_TDQSCKDL 614
MEM_LPDDR3_TDQSS_CYC 1.25
MEM_LPDDR3_TQSH_CYC 0.38
MEM_LPDDR3_TDSH_CYC 0.2
MEM_LPDDR3_TWLS_PS 175.0
MEM_LPDDR3_TWLH_PS 175.0
MEM_LPDDR3_TDSS_CYC 0.2
MEM_LPDDR3_TINIT_US 500
MEM_LPDDR3_TMRR_CK_CYC 4
MEM_LPDDR3_TMRW_CK_CYC 10
MEM_LPDDR3_TRAS_NS 42.5
MEM_LPDDR3_TRCD_NS 18.0
MEM_LPDDR3_TRP_NS 18.0
MEM_LPDDR3_TREFI_US 3.9
MEM_LPDDR3_TRFC_NS 210.0
MEM_LPDDR3_TWR_NS 15.0
MEM_LPDDR3_TWTR_CYC 6
MEM_LPDDR3_TFAW_NS 50.0
MEM_LPDDR3_TRRD_CYC 8
MEM_LPDDR3_TRTP_CYC 6
MEM_LPDDR3_TINIT_CK 499
MEM_LPDDR3_TDQSCK_DERV_PS 2
MEM_LPDDR3_TDQSCKDS 220
MEM_LPDDR3_TDQSCKDM 511
MEM_LPDDR3_TDQSCK_PS 5500
MEM_LPDDR3_TRAS_CYC 34
MEM_LPDDR3_TRCD_CYC 17
MEM_LPDDR3_TRP_CYC 17
MEM_LPDDR3_TRFC_CYC 168
MEM_LPDDR3_TWR_CYC 12
MEM_LPDDR3_TFAW_CYC 40
MEM_LPDDR3_TREFI_CYC 3120
MEM_LPDDR3_TRL_CYC 10
MEM_LPDDR3_TWL_CYC 6
BOARD_DDR3_USE_DEFAULT_SLEW_RATES true
BOARD_DDR3_USE_DEFAULT_ISI_VALUES true
BOARD_DDR3_USER_CK_SLEW_RATE 4.0
BOARD_DDR3_USER_AC_SLEW_RATE 2.0
BOARD_DDR3_USER_RCLK_SLEW_RATE 5.0
BOARD_DDR3_USER_WCLK_SLEW_RATE 4.0
BOARD_DDR3_USER_RDATA_SLEW_RATE 2.5
BOARD_DDR3_USER_WDATA_SLEW_RATE 2.0
BOARD_DDR3_USER_AC_ISI_NS 0.0
BOARD_DDR3_USER_RCLK_ISI_NS 0.0
BOARD_DDR3_USER_WCLK_ISI_NS 0.0
BOARD_DDR3_USER_RDATA_ISI_NS 0.0
BOARD_DDR3_USER_WDATA_ISI_NS 0.0
BOARD_DDR3_IS_SKEW_WITHIN_DQS_DESKEWED false
BOARD_DDR3_BRD_SKEW_WITHIN_DQS_NS 0.02
BOARD_DDR3_PKG_BRD_SKEW_WITHIN_DQS_NS 0.02
BOARD_DDR3_IS_SKEW_WITHIN_AC_DESKEWED true
BOARD_DDR3_BRD_SKEW_WITHIN_AC_NS 0.02
BOARD_DDR3_PKG_BRD_SKEW_WITHIN_AC_NS 0.02
BOARD_DDR3_DQS_TO_CK_SKEW_NS 0.02
BOARD_DDR3_SKEW_BETWEEN_DIMMS_NS 0.05
BOARD_DDR3_SKEW_BETWEEN_DQS_NS 0.02
BOARD_DDR3_AC_TO_CK_SKEW_NS 0.0
BOARD_DDR3_MAX_CK_DELAY_NS 0.6
BOARD_DDR3_MAX_DQS_DELAY_NS 0.6
BOARD_DDR3_TIS_DERATING_PS 0
BOARD_DDR3_TIH_DERATING_PS 0
BOARD_DDR3_TDS_DERATING_PS 0
BOARD_DDR3_TDH_DERATING_PS 0
BOARD_DDR3_CK_SLEW_RATE 4.0
BOARD_DDR3_AC_SLEW_RATE 2.0
BOARD_DDR3_RCLK_SLEW_RATE 5.0
BOARD_DDR3_WCLK_SLEW_RATE 4.0
BOARD_DDR3_RDATA_SLEW_RATE 2.5
BOARD_DDR3_WDATA_SLEW_RATE 2.0
BOARD_DDR3_AC_ISI_NS 0.0
BOARD_DDR3_RCLK_ISI_NS 0.0
BOARD_DDR3_WCLK_ISI_NS 0.0
BOARD_DDR3_RDATA_ISI_NS 0.0
BOARD_DDR3_WDATA_ISI_NS 0.0
BOARD_DDR3_SKEW_WITHIN_DQS_NS 0.0
BOARD_DDR3_SKEW_WITHIN_AC_NS 0.0
BOARD_DDR4_USE_DEFAULT_SLEW_RATES true
BOARD_DDR4_USE_DEFAULT_ISI_VALUES true
BOARD_DDR4_USER_CK_SLEW_RATE 4.0
BOARD_DDR4_USER_AC_SLEW_RATE 2.0
BOARD_DDR4_USER_RCLK_SLEW_RATE 8.0
BOARD_DDR4_USER_WCLK_SLEW_RATE 4.0
BOARD_DDR4_USER_RDATA_SLEW_RATE 4.0
BOARD_DDR4_USER_WDATA_SLEW_RATE 2.0
BOARD_DDR4_USER_AC_ISI_NS 0.0
BOARD_DDR4_USER_RCLK_ISI_NS 0.0
BOARD_DDR4_USER_WCLK_ISI_NS 0.0
BOARD_DDR4_USER_RDATA_ISI_NS 0.0
BOARD_DDR4_USER_WDATA_ISI_NS 0.0
BOARD_DDR4_IS_SKEW_WITHIN_DQS_DESKEWED true
BOARD_DDR4_BRD_SKEW_WITHIN_DQS_NS 0.02
BOARD_DDR4_PKG_BRD_SKEW_WITHIN_DQS_NS 0.02
BOARD_DDR4_IS_SKEW_WITHIN_AC_DESKEWED false
BOARD_DDR4_BRD_SKEW_WITHIN_AC_NS 0.02
BOARD_DDR4_PKG_BRD_SKEW_WITHIN_AC_NS 0.02
BOARD_DDR4_DQS_TO_CK_SKEW_NS 0.02
BOARD_DDR4_SKEW_BETWEEN_DIMMS_NS 0.05
BOARD_DDR4_SKEW_BETWEEN_DQS_NS 0.02
BOARD_DDR4_AC_TO_CK_SKEW_NS 0.0
BOARD_DDR4_MAX_CK_DELAY_NS 0.6
BOARD_DDR4_MAX_DQS_DELAY_NS 0.6
BOARD_DDR4_TIS_DERATING_PS 0
BOARD_DDR4_TIH_DERATING_PS 0
BOARD_DDR4_CK_SLEW_RATE 4.0
BOARD_DDR4_AC_SLEW_RATE 2.0
BOARD_DDR4_RCLK_SLEW_RATE 8.0
BOARD_DDR4_WCLK_SLEW_RATE 4.0
BOARD_DDR4_RDATA_SLEW_RATE 4.0
BOARD_DDR4_WDATA_SLEW_RATE 2.0
BOARD_DDR4_AC_ISI_NS 0.17
BOARD_DDR4_RCLK_ISI_NS 0.17
BOARD_DDR4_WCLK_ISI_NS 0.06
BOARD_DDR4_RDATA_ISI_NS 0.12
BOARD_DDR4_WDATA_ISI_NS 0.13
BOARD_DDR4_SKEW_WITHIN_DQS_NS 0.02
BOARD_DDR4_SKEW_WITHIN_AC_NS 0.18
BOARD_QDR2_USE_DEFAULT_SLEW_RATES true
BOARD_QDR2_USE_DEFAULT_ISI_VALUES true
BOARD_QDR2_USER_K_SLEW_RATE 4.0
BOARD_QDR2_USER_AC_SLEW_RATE 2.0
BOARD_QDR2_USER_RCLK_SLEW_RATE 4.0
BOARD_QDR2_USER_RDATA_SLEW_RATE 2.0
BOARD_QDR2_USER_WDATA_SLEW_RATE 2.0
BOARD_QDR2_USER_AC_ISI_NS 0.0
BOARD_QDR2_USER_RCLK_ISI_NS 0.0
BOARD_QDR2_USER_WCLK_ISI_NS 0.0
BOARD_QDR2_USER_RDATA_ISI_NS 0.0
BOARD_QDR2_USER_WDATA_ISI_NS 0.0
BOARD_QDR2_IS_SKEW_WITHIN_Q_DESKEWED false
BOARD_QDR2_IS_SKEW_WITHIN_D_DESKEWED false
BOARD_QDR2_IS_SKEW_WITHIN_AC_DESKEWED true
BOARD_QDR2_BRD_SKEW_WITHIN_Q_NS 0.02
BOARD_QDR2_BRD_SKEW_WITHIN_D_NS 0.02
BOARD_QDR2_BRD_SKEW_WITHIN_AC_NS 0.02
BOARD_QDR2_PKG_BRD_SKEW_WITHIN_Q_NS 0.02
BOARD_QDR2_PKG_BRD_SKEW_WITHIN_D_NS 0.02
BOARD_QDR2_PKG_BRD_SKEW_WITHIN_AC_NS 0.02
BOARD_QDR2_AC_TO_K_SKEW_NS 0.0
BOARD_QDR2_MAX_K_DELAY_NS 0.6
BOARD_QDR2_K_SLEW_RATE 4.0
BOARD_QDR2_AC_SLEW_RATE 2.0
BOARD_QDR2_RCLK_SLEW_RATE 4.0
BOARD_QDR2_WCLK_SLEW_RATE 4.0
BOARD_QDR2_RDATA_SLEW_RATE 2.0
BOARD_QDR2_WDATA_SLEW_RATE 2.0
BOARD_QDR2_AC_ISI_NS 0.0
BOARD_QDR2_RCLK_ISI_NS 0.0
BOARD_QDR2_WCLK_ISI_NS 0.0
BOARD_QDR2_RDATA_ISI_NS 0.0
BOARD_QDR2_WDATA_ISI_NS 0.0
BOARD_QDR2_SKEW_WITHIN_Q_NS 0.0
BOARD_QDR2_SKEW_WITHIN_D_NS 0.0
BOARD_QDR2_SKEW_WITHIN_AC_NS 0.0
BOARD_QDR4_USE_DEFAULT_SLEW_RATES true
BOARD_QDR4_USE_DEFAULT_ISI_VALUES true
BOARD_QDR4_USER_CK_SLEW_RATE 4.0
BOARD_QDR4_USER_AC_SLEW_RATE 2.0
BOARD_QDR4_USER_RCLK_SLEW_RATE 5.0
BOARD_QDR4_USER_WCLK_SLEW_RATE 4.0
BOARD_QDR4_USER_RDATA_SLEW_RATE 2.5
BOARD_QDR4_USER_WDATA_SLEW_RATE 2.0
BOARD_QDR4_USER_AC_ISI_NS 0.0
BOARD_QDR4_USER_RCLK_ISI_NS 0.0
BOARD_QDR4_USER_WCLK_ISI_NS 0.0
BOARD_QDR4_USER_RDATA_ISI_NS 0.0
BOARD_QDR4_USER_WDATA_ISI_NS 0.0
BOARD_QDR4_IS_SKEW_WITHIN_QK_DESKEWED true
BOARD_QDR4_BRD_SKEW_WITHIN_QK_NS 0.02
BOARD_QDR4_PKG_BRD_SKEW_WITHIN_QK_NS 0.02
BOARD_QDR4_IS_SKEW_WITHIN_AC_DESKEWED true
BOARD_QDR4_BRD_SKEW_WITHIN_AC_NS 0.02
BOARD_QDR4_PKG_BRD_SKEW_WITHIN_AC_NS 0.02
BOARD_QDR4_DK_TO_CK_SKEW_NS -0.02
BOARD_QDR4_SKEW_BETWEEN_DIMMS_NS 0.05
BOARD_QDR4_SKEW_BETWEEN_DK_NS 0.02
BOARD_QDR4_AC_TO_CK_SKEW_NS 0.0
BOARD_QDR4_MAX_CK_DELAY_NS 0.6
BOARD_QDR4_MAX_DK_DELAY_NS 0.6
BOARD_QDR4_CK_SLEW_RATE 4.0
BOARD_QDR4_AC_SLEW_RATE 2.0
BOARD_QDR4_RCLK_SLEW_RATE 5.0
BOARD_QDR4_WCLK_SLEW_RATE 4.0
BOARD_QDR4_RDATA_SLEW_RATE 2.5
BOARD_QDR4_WDATA_SLEW_RATE 2.0
BOARD_QDR4_AC_ISI_NS 0.0
BOARD_QDR4_RCLK_ISI_NS 0.0
BOARD_QDR4_WCLK_ISI_NS 0.0
BOARD_QDR4_RDATA_ISI_NS 0.0
BOARD_QDR4_WDATA_ISI_NS 0.0
BOARD_QDR4_SKEW_WITHIN_QK_NS 0.0
BOARD_QDR4_SKEW_WITHIN_AC_NS 0.0
BOARD_RLD3_USE_DEFAULT_SLEW_RATES true
BOARD_RLD3_USE_DEFAULT_ISI_VALUES true
BOARD_RLD3_USER_CK_SLEW_RATE 4.0
BOARD_RLD3_USER_AC_SLEW_RATE 2.0
BOARD_RLD3_USER_RCLK_SLEW_RATE 7.0
BOARD_RLD3_USER_WCLK_SLEW_RATE 4.0
BOARD_RLD3_USER_RDATA_SLEW_RATE 3.5
BOARD_RLD3_USER_WDATA_SLEW_RATE 2.0
BOARD_RLD3_USER_AC_ISI_NS 0.0
BOARD_RLD3_USER_RCLK_ISI_NS 0.0
BOARD_RLD3_USER_WCLK_ISI_NS 0.0
BOARD_RLD3_USER_RDATA_ISI_NS 0.0
BOARD_RLD3_USER_WDATA_ISI_NS 0.0
BOARD_RLD3_IS_SKEW_WITHIN_QK_DESKEWED false
BOARD_RLD3_BRD_SKEW_WITHIN_QK_NS 0.02
BOARD_RLD3_PKG_BRD_SKEW_WITHIN_QK_NS 0.02
BOARD_RLD3_IS_SKEW_WITHIN_AC_DESKEWED true
BOARD_RLD3_BRD_SKEW_WITHIN_AC_NS 0.02
BOARD_RLD3_PKG_BRD_SKEW_WITHIN_AC_NS 0.02
BOARD_RLD3_DK_TO_CK_SKEW_NS -0.02
BOARD_RLD3_SKEW_BETWEEN_DIMMS_NS 0.05
BOARD_RLD3_SKEW_BETWEEN_DK_NS 0.02
BOARD_RLD3_AC_TO_CK_SKEW_NS 0.0
BOARD_RLD3_MAX_CK_DELAY_NS 0.6
BOARD_RLD3_MAX_DK_DELAY_NS 0.6
BOARD_RLD3_TIS_DERATING_PS 0
BOARD_RLD3_TIH_DERATING_PS 0
BOARD_RLD3_TDS_DERATING_PS 0
BOARD_RLD3_TDH_DERATING_PS 0
BOARD_RLD3_CK_SLEW_RATE 4.0
BOARD_RLD3_AC_SLEW_RATE 2.0
BOARD_RLD3_RCLK_SLEW_RATE 7.0
BOARD_RLD3_WCLK_SLEW_RATE 4.0
BOARD_RLD3_RDATA_SLEW_RATE 3.5
BOARD_RLD3_WDATA_SLEW_RATE 2.0
BOARD_RLD3_AC_ISI_NS 0.0
BOARD_RLD3_RCLK_ISI_NS 0.0
BOARD_RLD3_WCLK_ISI_NS 0.0
BOARD_RLD3_RDATA_ISI_NS 0.0
BOARD_RLD3_WDATA_ISI_NS 0.0
BOARD_RLD3_SKEW_WITHIN_QK_NS 0.0
BOARD_RLD3_SKEW_WITHIN_AC_NS 0.0
BOARD_LPDDR3_USE_DEFAULT_SLEW_RATES true
BOARD_LPDDR3_USE_DEFAULT_ISI_VALUES true
BOARD_LPDDR3_USER_CK_SLEW_RATE 4.0
BOARD_LPDDR3_USER_AC_SLEW_RATE 2.0
BOARD_LPDDR3_USER_RCLK_SLEW_RATE 4.0
BOARD_LPDDR3_USER_WCLK_SLEW_RATE 4.0
BOARD_LPDDR3_USER_RDATA_SLEW_RATE 2.0
BOARD_LPDDR3_USER_WDATA_SLEW_RATE 2.0
BOARD_LPDDR3_USER_AC_ISI_NS 0.0
BOARD_LPDDR3_USER_RCLK_ISI_NS 0.0
BOARD_LPDDR3_USER_WCLK_ISI_NS 0.0
BOARD_LPDDR3_USER_RDATA_ISI_NS 0.0
BOARD_LPDDR3_USER_WDATA_ISI_NS 0.0
BOARD_LPDDR3_IS_SKEW_WITHIN_DQS_DESKEWED false
BOARD_LPDDR3_BRD_SKEW_WITHIN_DQS_NS 0.02
BOARD_LPDDR3_PKG_BRD_SKEW_WITHIN_DQS_NS 0.02
BOARD_LPDDR3_IS_SKEW_WITHIN_AC_DESKEWED true
BOARD_LPDDR3_BRD_SKEW_WITHIN_AC_NS 0.02
BOARD_LPDDR3_PKG_BRD_SKEW_WITHIN_AC_NS 0.02
BOARD_LPDDR3_DQS_TO_CK_SKEW_NS 0.02
BOARD_LPDDR3_SKEW_BETWEEN_DIMMS_NS 0.05
BOARD_LPDDR3_SKEW_BETWEEN_DQS_NS 0.02
BOARD_LPDDR3_AC_TO_CK_SKEW_NS 0.0
BOARD_LPDDR3_MAX_CK_DELAY_NS 0.6
BOARD_LPDDR3_MAX_DQS_DELAY_NS 0.6
BOARD_LPDDR3_TIS_DERATING_PS 0
BOARD_LPDDR3_TIH_DERATING_PS 0
BOARD_LPDDR3_TDS_DERATING_PS 0
BOARD_LPDDR3_TDH_DERATING_PS 0
BOARD_LPDDR3_CK_SLEW_RATE 4.0
BOARD_LPDDR3_AC_SLEW_RATE 2.0
BOARD_LPDDR3_RCLK_SLEW_RATE 4.0
BOARD_LPDDR3_WCLK_SLEW_RATE 4.0
BOARD_LPDDR3_RDATA_SLEW_RATE 2.0
BOARD_LPDDR3_WDATA_SLEW_RATE 2.0
BOARD_LPDDR3_AC_ISI_NS 0.0
BOARD_LPDDR3_RCLK_ISI_NS 0.0
BOARD_LPDDR3_WCLK_ISI_NS 0.0
BOARD_LPDDR3_RDATA_ISI_NS 0.0
BOARD_LPDDR3_WDATA_ISI_NS 0.0
BOARD_LPDDR3_SKEW_WITHIN_DQS_NS 0.0
BOARD_LPDDR3_SKEW_WITHIN_AC_NS 0.0
CTRL_ECC_EN false
CTRL_MMR_EN false
CTRL_AUTO_PRECHARGE_EN false
CTRL_USER_PRIORITY_EN false
CTRL_DDR3_AVL_PROTOCOL_ENUM CTRL_AVL_PROTOCOL_ST
CTRL_DDR3_SELF_REFRESH_EN false
CTRL_DDR3_AUTO_POWER_DOWN_EN false
CTRL_DDR3_AUTO_POWER_DOWN_CYCS 32
CTRL_DDR3_USER_REFRESH_EN false
CTRL_DDR3_USER_PRIORITY_EN false
CTRL_DDR3_AUTO_PRECHARGE_EN false
CTRL_DDR3_ADDR_ORDER_ENUM DDR3_CTRL_ADDR_ORDER_CS_R_B_C
CTRL_DDR3_ECC_EN false
CTRL_DDR3_ECC_AUTO_CORRECTION_EN false
CTRL_DDR3_REORDER_EN true
CTRL_DDR3_STARVE_LIMIT 10
CTRL_DDR3_MMR_EN false
CTRL_DDR3_RD_TO_WR_SAME_CHIP_DELTA_CYCS 0
CTRL_DDR3_WR_TO_RD_SAME_CHIP_DELTA_CYCS 0
CTRL_DDR3_RD_TO_RD_DIFF_CHIP_DELTA_CYCS 0
CTRL_DDR3_RD_TO_WR_DIFF_CHIP_DELTA_CYCS 0
CTRL_DDR3_WR_TO_WR_DIFF_CHIP_DELTA_CYCS 0
CTRL_DDR3_WR_TO_RD_DIFF_CHIP_DELTA_CYCS 0
CTRL_DDR4_AVL_PROTOCOL_ENUM CTRL_AVL_PROTOCOL_ST
CTRL_DDR4_SELF_REFRESH_EN false
CTRL_DDR4_AUTO_POWER_DOWN_EN false
CTRL_DDR4_AUTO_POWER_DOWN_CYCS 32
CTRL_DDR4_USER_REFRESH_EN false
CTRL_DDR4_USER_PRIORITY_EN false
CTRL_DDR4_AUTO_PRECHARGE_EN false
CTRL_DDR4_ADDR_ORDER_ENUM DDR4_CTRL_ADDR_ORDER_CS_R_B_C_BG
CTRL_DDR4_ECC_EN false
CTRL_DDR4_ECC_AUTO_CORRECTION_EN false
CTRL_DDR4_REORDER_EN true
CTRL_DDR4_STARVE_LIMIT 10
CTRL_DDR4_MMR_EN false
CTRL_DDR4_RD_TO_WR_SAME_CHIP_DELTA_CYCS 0
CTRL_DDR4_WR_TO_RD_SAME_CHIP_DELTA_CYCS 0
CTRL_DDR4_RD_TO_RD_DIFF_CHIP_DELTA_CYCS 0
CTRL_DDR4_RD_TO_WR_DIFF_CHIP_DELTA_CYCS 0
CTRL_DDR4_WR_TO_WR_DIFF_CHIP_DELTA_CYCS 0
CTRL_DDR4_WR_TO_RD_DIFF_CHIP_DELTA_CYCS 0
CTRL_QDR2_AVL_PROTOCOL_ENUM CTRL_AVL_PROTOCOL_MM
CTRL_QDR2_AVL_MAX_BURST_COUNT 4
CTRL_QDR2_AVL_ENABLE_POWER_OF_TWO_BUS false
CTRL_QDR2_AVL_SYMBOL_WIDTH 9
CTRL_QDR4_AVL_PROTOCOL_ENUM CTRL_AVL_PROTOCOL_MM
CTRL_QDR4_AVL_MAX_BURST_COUNT 4
CTRL_QDR4_AVL_ENABLE_POWER_OF_TWO_BUS false
CTRL_QDR4_ADD_RAW_TURNAROUND_DELAY_CYC 0
CTRL_QDR4_ADD_WAR_TURNAROUND_DELAY_CYC 0
CTRL_QDR4_AVL_SYMBOL_WIDTH 9
CTRL_QDR4_RAW_TURNAROUND_DELAY_CYC 4
CTRL_QDR4_WAR_TURNAROUND_DELAY_CYC 11
CTRL_RLD2_AVL_PROTOCOL_ENUM CTRL_AVL_PROTOCOL_MM
CTRL_RLD3_AVL_PROTOCOL_ENUM CTRL_AVL_PROTOCOL_MM
CTRL_RLD3_ADDR_ORDER_ENUM RLD3_CTRL_ADDR_ORDER_CS_R_B_C
CTRL_LPDDR3_AVL_PROTOCOL_ENUM CTRL_AVL_PROTOCOL_ST
CTRL_LPDDR3_SELF_REFRESH_EN false
CTRL_LPDDR3_AUTO_POWER_DOWN_EN false
CTRL_LPDDR3_AUTO_POWER_DOWN_CYCS 32
CTRL_LPDDR3_USER_REFRESH_EN false
CTRL_LPDDR3_USER_PRIORITY_EN false
CTRL_LPDDR3_AUTO_PRECHARGE_EN false
CTRL_LPDDR3_ADDR_ORDER_ENUM LPDDR3_CTRL_ADDR_ORDER_CS_R_B_C
CTRL_LPDDR3_REORDER_EN true
CTRL_LPDDR3_STARVE_LIMIT 10
CTRL_LPDDR3_MMR_EN false
CTRL_LPDDR3_RD_TO_WR_SAME_CHIP_DELTA_CYCS 0
CTRL_LPDDR3_WR_TO_RD_SAME_CHIP_DELTA_CYCS 0
CTRL_LPDDR3_RD_TO_RD_DIFF_CHIP_DELTA_CYCS 0
CTRL_LPDDR3_RD_TO_WR_DIFF_CHIP_DELTA_CYCS 0
CTRL_LPDDR3_WR_TO_WR_DIFF_CHIP_DELTA_CYCS 0
CTRL_LPDDR3_WR_TO_RD_DIFF_CHIP_DELTA_CYCS 0
DIAG_SIM_REGTEST_MODE false
DIAG_TIMING_REGTEST_MODE false
DIAG_SYNTH_FOR_SIM false
DIAG_FAST_SIM_OVERRIDE FAST_SIM_OVERRIDE_DEFAULT
DIAG_SEQ_RESET_AUTO_RELEASE avl
DIAG_DB_RESET_AUTO_RELEASE avl_release
DIAG_VERBOSE_IOAUX false
DIAG_ECLIPSE_DEBUG false
DIAG_EXPORT_VJI false
DIAG_ENABLE_JTAG_UART false
DIAG_ENABLE_JTAG_UART_HEX false
DIAG_ENABLE_HPS_EMIF_DEBUG false
DIAG_SOFT_NIOS_MODE SOFT_NIOS_MODE_DISABLED
DIAG_SOFT_NIOS_CLOCK_FREQUENCY 100
DIAG_USE_RS232_UART false
DIAG_RS232_UART_BAUDRATE 57600
DIAG_EX_DESIGN_ADD_TEST_EMIFS
DIAG_EX_DESIGN_SEPARATE_RESETS false
DIAG_EXPOSE_DFT_SIGNALS false
DIAG_EXTRA_CONFIGS
DIAG_USE_BOARD_DELAY_MODEL false
DIAG_BOARD_DELAY_CONFIG_STR
DIAG_TG_AVL_2_EXPORT_CFG_INTERFACE false
DIAG_TG_AVL_2_NUM_CFG_INTERFACES 0
DIAG_EXPORT_PLL_REF_CLK_OUT false
DIAG_EXPORT_PLL_LOCKED false
SHORT_QSYS_INTERFACE_NAMES false
DIAG_EXT_DOCS false
DIAG_SIM_CAL_MODE_ENUM SIM_CAL_MODE_SKIP
DIAG_EXPORT_SEQ_AVALON_SLAVE CAL_DEBUG_EXPORT_MODE_DISABLED
DIAG_EXPORT_SEQ_AVALON_MASTER false
DIAG_EX_DESIGN_NUM_OF_SLAVES 1
DIAG_EX_DESIGN_ISSP_EN true
DIAG_INTERFACE_ID 0
DIAG_EFFICIENCY_MONITOR EFFMON_MODE_DISABLED
DIAG_FAST_SIM true
DIAG_USE_TG_AVL_2 false
DIAG_INFI_TG2_ERR_TEST false
DIAG_USE_ABSTRACT_PHY false
DIAG_TG_DATA_PATTERN_LENGTH 8
DIAG_TG_BE_PATTERN_LENGTH 8
DIAG_BYPASS_DEFAULT_PATTERN false
DIAG_BYPASS_USER_STAGE true
DIAG_BYPASS_REPEAT_STAGE true
DIAG_BYPASS_STRESS_STAGE true
DIAG_ENABLE_SOFT_M20K false
DIAG_SIM_CHECKER_SKIP_TG false
DIAG_EX_DESIGN_SEPARATE_RZQS true
DIAG_DDR3_SIM_CAL_MODE_ENUM SIM_CAL_MODE_SKIP
DIAG_DDR3_EXPORT_SEQ_AVALON_SLAVE CAL_DEBUG_EXPORT_MODE_DISABLED
DIAG_DDR3_EXPORT_SEQ_AVALON_MASTER false
DIAG_DDR3_EX_DESIGN_NUM_OF_SLAVES 1
DIAG_DDR3_EX_DESIGN_ISSP_EN true
DIAG_DDR3_INTERFACE_ID 0
DIAG_DDR3_EFFICIENCY_MONITOR EFFMON_MODE_DISABLED
DIAG_DDR3_USE_TG_AVL_2 false
DIAG_DDR3_ABSTRACT_PHY false
DIAG_DDR3_BYPASS_DEFAULT_PATTERN false
DIAG_DDR3_BYPASS_USER_STAGE true
DIAG_DDR3_BYPASS_REPEAT_STAGE true
DIAG_DDR3_BYPASS_STRESS_STAGE true
DIAG_DDR3_INFI_TG2_ERR_TEST false
DIAG_DDR3_TG_DATA_PATTERN_LENGTH 8
DIAG_DDR3_TG_BE_PATTERN_LENGTH 8
DIAG_DDR3_SEPARATE_READ_WRITE_ITFS false
DIAG_DDR3_EX_DESIGN_SEPARATE_RZQS true
DIAG_DDR3_CA_LEVEL_EN false
DIAG_DDR3_CAL_ADDR0 0
DIAG_DDR3_CAL_ADDR1 8
DIAG_DDR3_CAL_ENABLE_NON_DES false
DIAG_DDR3_CAL_FULL_CAL_ON_RESET true
DIAG_DDR3_CAL_ENABLE_MICRON_AP false
DIAG_DDR4_SIM_CAL_MODE_ENUM SIM_CAL_MODE_SKIP
DIAG_DDR4_EXPORT_SEQ_AVALON_SLAVE CAL_DEBUG_EXPORT_MODE_DISABLED
DIAG_DDR4_EXPORT_SEQ_AVALON_MASTER false
DIAG_DDR4_EX_DESIGN_NUM_OF_SLAVES 1
DIAG_DDR4_EX_DESIGN_ISSP_EN true
DIAG_DDR4_INTERFACE_ID 0
DIAG_DDR4_EFFICIENCY_MONITOR EFFMON_MODE_DISABLED
DIAG_DDR4_USE_TG_AVL_2 false
DIAG_DDR4_ABSTRACT_PHY false
DIAG_DDR4_BYPASS_DEFAULT_PATTERN false
DIAG_DDR4_BYPASS_USER_STAGE true
DIAG_DDR4_BYPASS_REPEAT_STAGE true
DIAG_DDR4_BYPASS_STRESS_STAGE true
DIAG_DDR4_INFI_TG2_ERR_TEST false
DIAG_DDR4_TG_DATA_PATTERN_LENGTH 8
DIAG_DDR4_TG_BE_PATTERN_LENGTH 8
DIAG_DDR4_SEPARATE_READ_WRITE_ITFS false
DIAG_DDR4_EX_DESIGN_SEPARATE_RZQS true
DIAG_DDR4_SKIP_CA_LEVEL true
DIAG_DDR4_SKIP_CA_DESKEW false
DIAG_DDR4_SKIP_VREF_CAL false
DIAG_DDR4_CAL_ADDR0 0
DIAG_DDR4_CAL_ADDR1 8
DIAG_DDR4_CAL_ENABLE_NON_DES false
DIAG_DDR4_CAL_FULL_CAL_ON_RESET true
DIAG_QDR2_SIM_CAL_MODE_ENUM SIM_CAL_MODE_SKIP
DIAG_QDR2_EXPORT_SEQ_AVALON_SLAVE CAL_DEBUG_EXPORT_MODE_DISABLED
DIAG_QDR2_EXPORT_SEQ_AVALON_MASTER false
DIAG_QDR2_EX_DESIGN_NUM_OF_SLAVES 1
DIAG_QDR2_EX_DESIGN_ISSP_EN true
DIAG_QDR2_INTERFACE_ID 0
DIAG_QDR2_EFFICIENCY_MONITOR EFFMON_MODE_DISABLED
DIAG_QDR2_USE_TG_AVL_2 false
DIAG_QDR2_ABSTRACT_PHY false
DIAG_QDR2_BYPASS_DEFAULT_PATTERN false
DIAG_QDR2_BYPASS_USER_STAGE true
DIAG_QDR2_BYPASS_REPEAT_STAGE true
DIAG_QDR2_BYPASS_STRESS_STAGE true
DIAG_QDR2_INFI_TG2_ERR_TEST false
DIAG_QDR2_TG_DATA_PATTERN_LENGTH 8
DIAG_QDR2_TG_BE_PATTERN_LENGTH 8
DIAG_QDR2_SEPARATE_READ_WRITE_ITFS false
DIAG_QDR2_EX_DESIGN_SEPARATE_RZQS true
DIAG_QDR4_SIM_CAL_MODE_ENUM SIM_CAL_MODE_SKIP
DIAG_QDR4_EXPORT_SEQ_AVALON_SLAVE CAL_DEBUG_EXPORT_MODE_DISABLED
DIAG_QDR4_EXPORT_SEQ_AVALON_MASTER false
DIAG_QDR4_EX_DESIGN_NUM_OF_SLAVES 1
DIAG_QDR4_EX_DESIGN_ISSP_EN true
DIAG_QDR4_INTERFACE_ID 0
DIAG_QDR4_EFFICIENCY_MONITOR EFFMON_MODE_DISABLED
DIAG_QDR4_USE_TG_AVL_2 false
DIAG_QDR4_ABSTRACT_PHY false
DIAG_QDR4_BYPASS_DEFAULT_PATTERN false
DIAG_QDR4_BYPASS_USER_STAGE true
DIAG_QDR4_BYPASS_REPEAT_STAGE true
DIAG_QDR4_BYPASS_STRESS_STAGE true
DIAG_QDR4_INFI_TG2_ERR_TEST false
DIAG_QDR4_TG_DATA_PATTERN_LENGTH 8
DIAG_QDR4_TG_BE_PATTERN_LENGTH 8
DIAG_QDR4_SEPARATE_READ_WRITE_ITFS false
DIAG_QDR4_EX_DESIGN_SEPARATE_RZQS true
DIAG_QDR4_SKIP_VREF_CAL false
DIAG_RLD2_SIM_CAL_MODE_ENUM SIM_CAL_MODE_SKIP
DIAG_RLD2_EXPORT_SEQ_AVALON_SLAVE CAL_DEBUG_EXPORT_MODE_DISABLED
DIAG_RLD2_EXPORT_SEQ_AVALON_MASTER false
DIAG_RLD2_EX_DESIGN_NUM_OF_SLAVES 1
DIAG_RLD2_EX_DESIGN_ISSP_EN true
DIAG_RLD2_INTERFACE_ID 0
DIAG_RLD2_EFFICIENCY_MONITOR EFFMON_MODE_DISABLED
DIAG_RLD2_USE_TG_AVL_2 false
DIAG_RLD2_ABSTRACT_PHY false
DIAG_RLD2_BYPASS_DEFAULT_PATTERN false
DIAG_RLD2_BYPASS_USER_STAGE true
DIAG_RLD2_BYPASS_REPEAT_STAGE true
DIAG_RLD2_BYPASS_STRESS_STAGE true
DIAG_RLD2_INFI_TG2_ERR_TEST false
DIAG_RLD2_TG_DATA_PATTERN_LENGTH 8
DIAG_RLD2_TG_BE_PATTERN_LENGTH 8
DIAG_RLD2_SEPARATE_READ_WRITE_ITFS false
DIAG_RLD2_EX_DESIGN_SEPARATE_RZQS true
DIAG_RLD3_SIM_CAL_MODE_ENUM SIM_CAL_MODE_SKIP
DIAG_RLD3_EXPORT_SEQ_AVALON_SLAVE CAL_DEBUG_EXPORT_MODE_DISABLED
DIAG_RLD3_EXPORT_SEQ_AVALON_MASTER false
DIAG_RLD3_EX_DESIGN_NUM_OF_SLAVES 1
DIAG_RLD3_EX_DESIGN_ISSP_EN true
DIAG_RLD3_INTERFACE_ID 0
DIAG_RLD3_EFFICIENCY_MONITOR EFFMON_MODE_DISABLED
DIAG_RLD3_USE_TG_AVL_2 false
DIAG_RLD3_ABSTRACT_PHY false
DIAG_RLD3_BYPASS_DEFAULT_PATTERN false
DIAG_RLD3_BYPASS_USER_STAGE true
DIAG_RLD3_BYPASS_REPEAT_STAGE true
DIAG_RLD3_BYPASS_STRESS_STAGE true
DIAG_RLD3_INFI_TG2_ERR_TEST false
DIAG_RLD3_TG_DATA_PATTERN_LENGTH 8
DIAG_RLD3_TG_BE_PATTERN_LENGTH 8
DIAG_RLD3_SEPARATE_READ_WRITE_ITFS false
DIAG_RLD3_EX_DESIGN_SEPARATE_RZQS true
DIAG_LPDDR3_SIM_CAL_MODE_ENUM SIM_CAL_MODE_SKIP
DIAG_LPDDR3_EXPORT_SEQ_AVALON_SLAVE CAL_DEBUG_EXPORT_MODE_DISABLED
DIAG_LPDDR3_EXPORT_SEQ_AVALON_MASTER false
DIAG_LPDDR3_EX_DESIGN_NUM_OF_SLAVES 1
DIAG_LPDDR3_EX_DESIGN_ISSP_EN true
DIAG_LPDDR3_INTERFACE_ID 0
DIAG_LPDDR3_EFFICIENCY_MONITOR EFFMON_MODE_DISABLED
DIAG_LPDDR3_USE_TG_AVL_2 false
DIAG_LPDDR3_ABSTRACT_PHY false
DIAG_LPDDR3_BYPASS_DEFAULT_PATTERN false
DIAG_LPDDR3_BYPASS_USER_STAGE true
DIAG_LPDDR3_BYPASS_REPEAT_STAGE true
DIAG_LPDDR3_BYPASS_STRESS_STAGE true
DIAG_LPDDR3_INFI_TG2_ERR_TEST false
DIAG_LPDDR3_TG_DATA_PATTERN_LENGTH 8
DIAG_LPDDR3_TG_BE_PATTERN_LENGTH 8
DIAG_LPDDR3_SEPARATE_READ_WRITE_ITFS false
DIAG_LPDDR3_EX_DESIGN_SEPARATE_RZQS true
DIAG_LPDDR3_SKIP_CA_LEVEL false
DIAG_LPDDR3_SKIP_CA_DESKEW false
EX_DESIGN_GUI_GEN_SIM false
EX_DESIGN_GUI_GEN_SYNTH false
EX_DESIGN_GUI_TARGET_DEV_KIT TARGET_DEV_KIT_NONE
EX_DESIGN_GUI_PREV_PRESET TARGET_DEV_KIT_NONE
EX_DESIGN_GUI_DDR3_SEL_DESIGN AVAIL_EX_DESIGNS_GEN_DESIGN
EX_DESIGN_GUI_DDR3_GEN_SIM true
EX_DESIGN_GUI_DDR3_GEN_SYNTH true
EX_DESIGN_GUI_DDR3_HDL_FORMAT HDL_FORMAT_VERILOG
EX_DESIGN_GUI_DDR3_TARGET_DEV_KIT TARGET_DEV_KIT_NONE
EX_DESIGN_GUI_DDR3_PREV_PRESET TARGET_DEV_KIT_NONE
EX_DESIGN_GUI_DDR4_SEL_DESIGN AVAIL_EX_DESIGNS_GEN_DESIGN
EX_DESIGN_GUI_DDR4_GEN_SIM true
EX_DESIGN_GUI_DDR4_GEN_SYNTH true
EX_DESIGN_GUI_DDR4_HDL_FORMAT HDL_FORMAT_VERILOG
EX_DESIGN_GUI_DDR4_TARGET_DEV_KIT TARGET_DEV_KIT_NONE
EX_DESIGN_GUI_DDR4_PREV_PRESET TARGET_DEV_KIT_NONE
EX_DESIGN_GUI_QDR2_SEL_DESIGN AVAIL_EX_DESIGNS_GEN_DESIGN
EX_DESIGN_GUI_QDR2_GEN_SIM true
EX_DESIGN_GUI_QDR2_GEN_SYNTH true
EX_DESIGN_GUI_QDR2_HDL_FORMAT HDL_FORMAT_VERILOG
EX_DESIGN_GUI_QDR2_TARGET_DEV_KIT TARGET_DEV_KIT_NONE
EX_DESIGN_GUI_QDR2_PREV_PRESET TARGET_DEV_KIT_NONE
EX_DESIGN_GUI_QDR4_SEL_DESIGN AVAIL_EX_DESIGNS_GEN_DESIGN
EX_DESIGN_GUI_QDR4_GEN_SIM true
EX_DESIGN_GUI_QDR4_GEN_SYNTH true
EX_DESIGN_GUI_QDR4_HDL_FORMAT HDL_FORMAT_VERILOG
EX_DESIGN_GUI_QDR4_TARGET_DEV_KIT TARGET_DEV_KIT_NONE
EX_DESIGN_GUI_QDR4_PREV_PRESET TARGET_DEV_KIT_NONE
EX_DESIGN_GUI_RLD2_SEL_DESIGN AVAIL_EX_DESIGNS_GEN_DESIGN
EX_DESIGN_GUI_RLD2_GEN_SIM true
EX_DESIGN_GUI_RLD2_GEN_SYNTH true
EX_DESIGN_GUI_RLD2_HDL_FORMAT HDL_FORMAT_VERILOG
EX_DESIGN_GUI_RLD2_TARGET_DEV_KIT TARGET_DEV_KIT_NONE
EX_DESIGN_GUI_RLD2_PREV_PRESET TARGET_DEV_KIT_NONE
EX_DESIGN_GUI_RLD3_SEL_DESIGN AVAIL_EX_DESIGNS_GEN_DESIGN
EX_DESIGN_GUI_RLD3_GEN_SIM true
EX_DESIGN_GUI_RLD3_GEN_SYNTH true
EX_DESIGN_GUI_RLD3_HDL_FORMAT HDL_FORMAT_VERILOG
EX_DESIGN_GUI_RLD3_TARGET_DEV_KIT TARGET_DEV_KIT_NONE
EX_DESIGN_GUI_RLD3_PREV_PRESET TARGET_DEV_KIT_NONE
EX_DESIGN_GUI_LPDDR3_SEL_DESIGN AVAIL_EX_DESIGNS_GEN_DESIGN
EX_DESIGN_GUI_LPDDR3_GEN_SIM true
EX_DESIGN_GUI_LPDDR3_GEN_SYNTH true
EX_DESIGN_GUI_LPDDR3_HDL_FORMAT HDL_FORMAT_VERILOG
EX_DESIGN_GUI_LPDDR3_TARGET_DEV_KIT TARGET_DEV_KIT_NONE
EX_DESIGN_GUI_LPDDR3_PREV_PRESET TARGET_DEV_KIT_NONE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)
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