subsys_pcie_clk_125

2017.05.02.01:01:32 Datasheet
Overview

Memory Map

clk_125

altera_clock_bridge v17.0


Parameters

DERIVED_CLOCK_RATE 0
EXPLICIT_CLOCK_RATE 125000000
NUM_CLOCK_OUTPUTS 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)
generation took 0.00 seconds rendering took 0.00 seconds