subsys_pcie_coreclk_out
2017.05.02.01:01:54
Datasheet
Overview
Memory Map
coreclk_out
altera_clock_bridge v17.0
Parameters
DERIVED_CLOCK_RATE
250000000
EXPLICIT_CLOCK_RATE
250000000
NUM_CLOCK_OUTPUTS
1
deviceFamily
UNKNOWN
generateLegacySim
false
Software Assignments
(none)
generation took 0.00 seconds
rendering took 0.00 seconds