interface_type_hwtcl |
Avalon-MM |
force_tag_checking_on_hwtcl |
0 |
app_interface_width_hwtcl |
128-bit |
wrala_hwtcl |
7 |
device_family |
ARRIA10 |
base_device |
NIGHTFURY4 |
part_trait_device |
10AS066N3F40E2SG |
opn |
Rev D |
eco_fb332688_dis |
true |
bar0_address_width_mux_hwtcl |
32 |
bar1_address_width_mux_hwtcl |
0 |
bar2_address_width_mux_hwtcl |
0 |
bar3_address_width_mux_hwtcl |
0 |
bar4_address_width_mux_hwtcl |
0 |
bar5_address_width_mux_hwtcl |
0 |
st_signal_width_integer_hwtcl |
1 |
data_width_integer_hwtcl |
128 |
data_width_integer_rxm_txs_hwtcl |
128 |
data_width_integer_txs_hwtcl |
128 |
data_byte_width_integer_hwtcl |
16 |
reconfig_address_width_integer_hwtcl |
13 |
data_byte_width_integer_rxm_txs_hwtcl |
16 |
data_byte_width_integer_txs_hwtcl |
16 |
burst_count_integer_hwtcl |
6 |
empty_integer_hwtcl |
1 |
port_type_integer_hwtcl |
1 |
link_width_integer_hwtcl |
8 |
lane_rate_integer_hwtcl |
2 |
pld_clk_mhz_integer_hwtcl |
2500 |
bar0_type_integer_hwtcl |
1 |
bar1_type_integer_hwtcl |
0 |
bar2_type_integer_hwtcl |
0 |
bar3_type_integer_hwtcl |
0 |
bar4_type_integer_hwtcl |
0 |
bar5_type_integer_hwtcl |
0 |
include_dma_hwtcl |
0 |
txs_addr_width_integer_hwtcl |
28 |
interface_type_integer_hwtcl |
1 |
dma_width_hwtcl |
128 |
dma_be_width_hwtcl |
16 |
dma_brst_cnt_w_hwtcl |
6 |
set_embedded_debug_enable_hwtcl |
1 |
set_capability_reg_enable_hwtcl |
1 |
set_csr_soft_logic_enable_hwtcl |
0 |
set_prbs_soft_logic_enable_hwtcl |
0 |
rcfg_jtag_enable_hwtcl |
1 |
cpl_spc_header_hwtcl |
112 |
cpl_spc_data_hwtcl |
440 |
avmm_addr_width_hwtcl |
32 |
cb_pcie_mode_hwtcl |
0 |
cb_pcie_rx_lite_hwtcl |
0 |
cg_impl_cra_av_slave_port_hwtcl |
1 |
cg_enable_advanced_interrupt_hwtcl |
0 |
cg_enable_a2p_interrupt_hwtcl |
0 |
enable_hip_status_for_avmm_hwtcl |
1 |
internal_controller_hwtcl |
1 |
enable_rxm_burst_hwtcl |
0 |
extended_tag_support_hwtcl |
0 |
user_txs_addr_width_hwtcl |
22 |
cg_a2p_addr_map_num_entries_hwtcl |
2 |
cg_a2p_addr_map_pass_thru_bits_hwtcl |
27 |
link_width_hwtcl |
x8 |
lane_rate_hwtcl |
Gen2 (5.0 Gbps) |
port_type_hwtcl |
Root port |
pcie_spec_version_hwtcl |
3.0 |
rx_buffer_credit_alloc_hwtcl |
Balanced |
rx_buffer_post_credit_alloc_display |
Header:n/a Data:n/a |
rx_buffer_nonpost_credit_alloc_display |
Header:n/a Data:n/a |
rx_buffer_credit_alloc_display |
Header:112 Data:440 |
rx_cred_ctl_param_hwtcl |
0 |
pll_refclk_freq_hwtcl |
100 MHz |
set_pld_clk_x1_625MHz_hwtcl |
0 |
enable_avst_reset_hwtcl |
1 |
use_rx_st_be_hwtcl |
0 |
use_ast_parity_hwtcl |
0 |
multiple_packets_per_cycle_hwtcl |
0 |
cvp_enable_hwtcl |
0 |
use_tx_cons_cred_sel_hwtcl |
0 |
cseb_config_bypass_hwtcl |
0 |
cseb_autonomous_hwtcl |
0 |
speed_change_hwtcl |
0 |
hip_reconfig_hwtcl |
0 |
xcvr_reconfig_hwtcl |
0 |
export_fpll_output_to_top_level_hwtcl |
0 |
export_phy_input_to_top_level_hwtcl |
0 |
enable_lmi_hwtcl |
0 |
adme_enable_hwtcl |
1 |
enable_devkit_conduit_hwtcl |
0 |
enable_skp_det |
0 |
dis_adapt |
0 |
select_design_example_hwtcl |
PIO |
enable_example_design_qii_hwtcl |
1 |
enable_example_design_sim_hwtcl |
1 |
enable_example_design_synth_hwtcl |
1 |
enable_example_design_tb_hwtcl |
1 |
apps_type_hwtcl |
0 |
select_design_example_rtl_lang_hwtcl |
Verilog |
targeted_devkit_hwtcl |
Arria 10 GX FPGA Development Kit |
bar0_type_hwtcl |
64-bit prefetchable memory |
bar0_address_width_hwtcl |
16 |
bar1_type_hwtcl |
Disabled |
bar1_address_width_hwtcl |
0 |
bar2_type_hwtcl |
Disabled |
bar2_address_width_hwtcl |
0 |
bar3_type_hwtcl |
Disabled |
bar3_address_width_hwtcl |
0 |
bar4_type_hwtcl |
Disabled |
bar4_address_width_hwtcl |
0 |
bar5_type_hwtcl |
Disabled |
bar5_address_width_hwtcl |
0 |
expansion_base_address_register_hwtcl |
0 |
bar0_address_width_avmm_hwtcl |
32 |
bar1_address_width_avmm_hwtcl |
0 |
bar2_address_width_avmm_hwtcl |
0 |
bar3_address_width_avmm_hwtcl |
0 |
bar4_address_width_avmm_hwtcl |
0 |
bar5_address_width_avmm_hwtcl |
0 |
io_window_addr_width_hwtcl |
0 |
prefetchable_mem_window_addr_width_hwtcl |
0 |
vendor_id_hwtcl |
4466 |
device_id_hwtcl |
57344 |
pf0_vf_device_id_hwtcl |
0 |
revision_id_hwtcl |
1 |
class_code_hwtcl |
394240 |
pf0_subclass_code_hwtcl |
0 |
pf0_pci_prog_intfc_byte_hwtcl |
0 |
subsystem_vendor_id_hwtcl |
4466 |
subsystem_device_id_hwtcl |
57344 |
maximum_payload_size_hwtcl |
256 |
extended_tag_field_hwtcl |
32 |
completion_timeout_hwtcl |
ABCD |
completion_timeout_disable_hwtcl |
1 |
enable_completion_timeout_disable_hwtcl |
1 |
advance_error_reporting_hwtcl |
1 |
ecrc_check_capable_hwtcl |
0 |
ecrc_gen_capable_hwtcl |
0 |
use_crc_forwarding_hwtcl |
0 |
track_rxfc_cplbuf_ovf_hwtcl |
0 |
port_link_number_hwtcl |
1 |
dll_active_report_support_hwtcl |
0 |
surprise_down_error_support_hwtcl |
0 |
slot_clock_cfg_hwtcl |
1 |
msi_multi_message_capable_hwtcl |
4 |
vsec_id_hwtcl |
4466 |
vsec_cap_hwtcl |
0 |
user_id_hwtcl |
0 |
enable_function_msix_support_hwtcl |
0 |
msix_table_size_hwtcl |
0 |
msix_table_offset_hwtcl |
0 |
msix_table_bir_hwtcl |
0 |
msix_pba_offset_hwtcl |
0 |
msix_pba_bir_hwtcl |
0 |
enable_slot_register_hwtcl |
0 |
slot_power_scale_hwtcl |
0 |
slot_power_limit_hwtcl |
0 |
slot_number_hwtcl |
0 |
endpoint_l0_latency_hwtcl |
0 |
endpoint_l1_latency_hwtcl |
0 |
deemphasis_enable_hwtcl |
0 |
gen3_coeff_1_hwtcl |
8 |
bfm_drive_interface_clk_hwtcl |
1 |
bfm_drive_interface_npor_hwtcl |
1 |
bfm_drive_interface_pipe_hwtcl |
1 |
bfm_drive_interface_control_hwtcl |
1 |
serial_sim_hwtcl |
1 |
enable_pipe32_phyip_ser_driver_hwtcl |
0 |
cseb_extend_pci_hwtcl |
0 |
cseb_extend_pcie_hwtcl |
0 |
reserved_debug_hwtcl |
0 |
include_sriov_hwtcl |
0 |
app_msi_req_fn_hwtcl |
8 |
cfg_num_vf_width_hwtcl |
8 |
flr_completed_vf_width_hwtcl |
4 |
sriov2_en |
1 |
sriov2_exprom_en_hwtcl |
0 |
enable_nobar_slection_hwtcl |
0 |
enable_custom_features_hwtcl |
0 |
pf0_extra_bar_present_hwtcl |
0 |
pf0_extra_bar_size_hwtcl |
12 |
devhide_support_hwtcl |
0 |
device_embedded_ep_support_hwtcl |
0 |
total_pf_count_hwtcl |
1 |
pf0_vf_count_user_hwtcl |
0 |
pf1_vf_count_user_hwtcl |
0 |
pf2_vf_count_user_hwtcl |
0 |
pf3_vf_count_user_hwtcl |
0 |
pf0_vf_count_hwtcl |
0 |
pf1_vf_count_hwtcl |
0 |
pf2_vf_count_hwtcl |
0 |
pf3_vf_count_hwtcl |
0 |
total_vf_count_hwtcl |
4 |
total_pf_count_width_hwtcl |
1 |
total_vf_count_width_hwtcl |
1 |
system_page_sizes_supported_hwtcl |
1363 |
sr_iov_support_hwtcl |
0 |
ari_support_hwtcl |
0 |
flr_capability_user_hwtcl |
0 |
flr_capability_hwtcl |
0 |
pf_tph_support_hwtcl |
0 |
pf0_tph_int_mode_support_hwtcl |
0 |
pf0_tph_dev_specific_mode_support_hwtcl |
0 |
pf0_tph_st_table_location_hwtcl |
0 |
pf0_tph_st_table_size_hwtcl |
63 |
pf1_tph_int_mode_support_hwtcl |
0 |
pf1_tph_dev_specific_mode_support_hwtcl |
0 |
pf1_tph_st_table_location_hwtcl |
0 |
pf1_tph_st_table_size_hwtcl |
63 |
pf2_tph_int_mode_support_hwtcl |
0 |
pf2_tph_dev_specific_mode_support_hwtcl |
0 |
pf2_tph_st_table_location_hwtcl |
0 |
pf2_tph_st_table_size_hwtcl |
63 |
pf3_tph_int_mode_support_hwtcl |
0 |
pf3_tph_dev_specific_mode_support_hwtcl |
0 |
pf3_tph_st_table_location_hwtcl |
0 |
pf3_tph_st_table_size_hwtcl |
63 |
vf_tph_support_hwtcl |
0 |
pf0_vf_tph_int_mode_support_hwtcl |
0 |
pf0_vf_tph_dev_specific_mode_support_hwtcl |
0 |
pf0_vf_tph_st_table_location_hwtcl |
0 |
pf0_vf_tph_st_table_size_hwtcl |
63 |
pf1_vf_tph_int_mode_support_hwtcl |
0 |
pf1_vf_tph_dev_specific_mode_support_hwtcl |
0 |
pf1_vf_tph_st_table_location_hwtcl |
0 |
pf1_vf_tph_st_table_size_hwtcl |
63 |
pf2_vf_tph_int_mode_support_hwtcl |
0 |
pf2_vf_tph_dev_specific_mode_support_hwtcl |
0 |
pf2_vf_tph_st_table_location_hwtcl |
0 |
pf2_vf_tph_st_table_size_hwtcl |
63 |
pf3_vf_tph_int_mode_support_hwtcl |
0 |
pf3_vf_tph_dev_specific_mode_support_hwtcl |
0 |
pf3_vf_tph_st_table_location_hwtcl |
0 |
pf3_vf_tph_st_table_size_hwtcl |
63 |
pf_ats_support_hwtcl |
0 |
pf0_ats_invalidate_queue_depth_hwtcl |
0 |
pf1_ats_invalidate_queue_depth_hwtcl |
0 |
pf2_ats_invalidate_queue_depth_hwtcl |
0 |
pf3_ats_invalidate_queue_depth_hwtcl |
0 |
vf_ats_support_hwtcl |
0 |
pf0_bar0_present_hwtcl |
1 |
pf0_bar1_present_hwtcl |
0 |
pf0_bar2_present_hwtcl |
0 |
pf0_bar3_present_hwtcl |
0 |
pf0_bar4_present_hwtcl |
0 |
pf0_bar5_present_hwtcl |
0 |
pf0_exprom_bar_present_hwtcl |
0 |
pf0_bar0_type_hwtcl |
1 |
pf0_bar2_type_hwtcl |
1 |
pf0_bar4_type_hwtcl |
1 |
pf0_bar0_prefetchable_hwtcl |
1 |
pf0_bar1_prefetchable_hwtcl |
1 |
pf0_bar2_prefetchable_hwtcl |
1 |
pf0_bar3_prefetchable_hwtcl |
1 |
pf0_bar4_prefetchable_hwtcl |
1 |
pf0_bar5_prefetchable_hwtcl |
1 |
pf0_bar0_size_hwtcl |
12 |
pf0_bar1_size_hwtcl |
12 |
pf0_bar2_size_hwtcl |
12 |
pf0_bar3_size_hwtcl |
12 |
pf0_bar4_size_hwtcl |
12 |
pf0_bar5_size_hwtcl |
12 |
pf0_exprom_bar_size_hwtcl |
12 |
pf0_vf_bar0_present_hwtcl |
0 |
pf0_vf_bar1_present_hwtcl |
0 |
pf0_vf_bar2_present_hwtcl |
0 |
pf0_vf_bar3_present_hwtcl |
0 |
pf0_vf_bar4_present_hwtcl |
0 |
pf0_vf_bar5_present_hwtcl |
0 |
pf0_vf_bar0_type_hwtcl |
1 |
pf0_vf_bar2_type_hwtcl |
1 |
pf0_vf_bar4_type_hwtcl |
1 |
pf0_vf_bar0_prefetchable_hwtcl |
1 |
pf0_vf_bar1_prefetchable_hwtcl |
1 |
pf0_vf_bar2_prefetchable_hwtcl |
1 |
pf0_vf_bar3_prefetchable_hwtcl |
1 |
pf0_vf_bar4_prefetchable_hwtcl |
1 |
pf0_vf_bar5_prefetchable_hwtcl |
1 |
pf0_vf_bar0_size_hwtcl |
12 |
pf0_vf_bar1_size_hwtcl |
12 |
pf0_vf_bar2_size_hwtcl |
12 |
pf0_vf_bar3_size_hwtcl |
12 |
pf0_vf_bar4_size_hwtcl |
12 |
pf0_vf_bar5_size_hwtcl |
12 |
pf1_bar0_present_hwtcl |
0 |
pf1_bar1_present_hwtcl |
0 |
pf1_bar2_present_hwtcl |
0 |
pf1_bar3_present_hwtcl |
0 |
pf1_bar4_present_hwtcl |
0 |
pf1_bar5_present_hwtcl |
0 |
pf1_exprom_bar_present_hwtcl |
0 |
pf1_bar0_type_hwtcl |
1 |
pf1_bar2_type_hwtcl |
1 |
pf1_bar4_type_hwtcl |
1 |
pf1_bar0_prefetchable_hwtcl |
1 |
pf1_bar1_prefetchable_hwtcl |
1 |
pf1_bar2_prefetchable_hwtcl |
1 |
pf1_bar3_prefetchable_hwtcl |
1 |
pf1_bar4_prefetchable_hwtcl |
1 |
pf1_bar5_prefetchable_hwtcl |
1 |
pf1_bar0_size_hwtcl |
12 |
pf1_bar1_size_hwtcl |
12 |
pf1_bar2_size_hwtcl |
12 |
pf1_bar3_size_hwtcl |
12 |
pf1_bar4_size_hwtcl |
12 |
pf1_bar5_size_hwtcl |
12 |
pf1_exprom_bar_size_hwtcl |
12 |
pf1_vf_bar0_present_hwtcl |
0 |
pf1_vf_bar1_present_hwtcl |
0 |
pf1_vf_bar2_present_hwtcl |
0 |
pf1_vf_bar3_present_hwtcl |
0 |
pf1_vf_bar4_present_hwtcl |
0 |
pf1_vf_bar5_present_hwtcl |
0 |
pf1_vf_bar0_type_hwtcl |
1 |
pf1_vf_bar2_type_hwtcl |
1 |
pf1_vf_bar4_type_hwtcl |
1 |
pf1_vf_bar0_prefetchable_hwtcl |
1 |
pf1_vf_bar1_prefetchable_hwtcl |
1 |
pf1_vf_bar2_prefetchable_hwtcl |
1 |
pf1_vf_bar3_prefetchable_hwtcl |
1 |
pf1_vf_bar4_prefetchable_hwtcl |
1 |
pf1_vf_bar5_prefetchable_hwtcl |
1 |
pf1_vf_bar0_size_hwtcl |
12 |
pf1_vf_bar1_size_hwtcl |
12 |
pf1_vf_bar2_size_hwtcl |
12 |
pf1_vf_bar3_size_hwtcl |
12 |
pf1_vf_bar4_size_hwtcl |
12 |
pf1_vf_bar5_size_hwtcl |
12 |
pf2_bar0_present_hwtcl |
0 |
pf2_bar1_present_hwtcl |
0 |
pf2_bar2_present_hwtcl |
0 |
pf2_bar3_present_hwtcl |
0 |
pf2_bar4_present_hwtcl |
0 |
pf2_bar5_present_hwtcl |
0 |
pf2_exprom_bar_present_hwtcl |
0 |
pf2_bar0_type_hwtcl |
1 |
pf2_bar2_type_hwtcl |
1 |
pf2_bar4_type_hwtcl |
1 |
pf2_bar0_prefetchable_hwtcl |
1 |
pf2_bar1_prefetchable_hwtcl |
1 |
pf2_bar2_prefetchable_hwtcl |
1 |
pf2_bar3_prefetchable_hwtcl |
1 |
pf2_bar4_prefetchable_hwtcl |
1 |
pf2_bar5_prefetchable_hwtcl |
1 |
pf2_bar0_size_hwtcl |
12 |
pf2_bar1_size_hwtcl |
12 |
pf2_bar2_size_hwtcl |
12 |
pf2_bar3_size_hwtcl |
12 |
pf2_bar4_size_hwtcl |
12 |
pf2_bar5_size_hwtcl |
12 |
pf2_exprom_bar_size_hwtcl |
12 |
pf2_vf_bar0_present_hwtcl |
0 |
pf2_vf_bar1_present_hwtcl |
0 |
pf2_vf_bar2_present_hwtcl |
0 |
pf2_vf_bar3_present_hwtcl |
0 |
pf2_vf_bar4_present_hwtcl |
0 |
pf2_vf_bar5_present_hwtcl |
0 |
pf2_vf_bar0_type_hwtcl |
1 |
pf2_vf_bar2_type_hwtcl |
1 |
pf2_vf_bar4_type_hwtcl |
1 |
pf2_vf_bar0_prefetchable_hwtcl |
1 |
pf2_vf_bar1_prefetchable_hwtcl |
1 |
pf2_vf_bar2_prefetchable_hwtcl |
1 |
pf2_vf_bar3_prefetchable_hwtcl |
1 |
pf2_vf_bar4_prefetchable_hwtcl |
1 |
pf2_vf_bar5_prefetchable_hwtcl |
1 |
pf2_vf_bar0_size_hwtcl |
12 |
pf2_vf_bar1_size_hwtcl |
12 |
pf2_vf_bar2_size_hwtcl |
12 |
pf2_vf_bar3_size_hwtcl |
12 |
pf2_vf_bar4_size_hwtcl |
12 |
pf2_vf_bar5_size_hwtcl |
12 |
pf3_bar0_present_hwtcl |
0 |
pf3_bar1_present_hwtcl |
0 |
pf3_bar2_present_hwtcl |
0 |
pf3_bar3_present_hwtcl |
0 |
pf3_bar4_present_hwtcl |
0 |
pf3_bar5_present_hwtcl |
0 |
pf3_exprom_bar_present_hwtcl |
0 |
pf3_bar0_type_hwtcl |
1 |
pf3_bar2_type_hwtcl |
1 |
pf3_bar4_type_hwtcl |
1 |
pf3_bar0_prefetchable_hwtcl |
1 |
pf3_bar1_prefetchable_hwtcl |
1 |
pf3_bar2_prefetchable_hwtcl |
1 |
pf3_bar3_prefetchable_hwtcl |
1 |
pf3_bar4_prefetchable_hwtcl |
1 |
pf3_bar5_prefetchable_hwtcl |
1 |
pf3_bar0_size_hwtcl |
12 |
pf3_bar1_size_hwtcl |
12 |
pf3_bar2_size_hwtcl |
12 |
pf3_bar3_size_hwtcl |
12 |
pf3_bar4_size_hwtcl |
12 |
pf3_bar5_size_hwtcl |
12 |
pf3_exprom_bar_size_hwtcl |
12 |
pf3_vf_bar0_present_hwtcl |
0 |
pf3_vf_bar1_present_hwtcl |
0 |
pf3_vf_bar2_present_hwtcl |
0 |
pf3_vf_bar3_present_hwtcl |
0 |
pf3_vf_bar4_present_hwtcl |
0 |
pf3_vf_bar5_present_hwtcl |
0 |
pf3_vf_bar0_type_hwtcl |
1 |
pf3_vf_bar2_type_hwtcl |
1 |
pf3_vf_bar4_type_hwtcl |
1 |
pf3_vf_bar0_prefetchable_hwtcl |
1 |
pf3_vf_bar1_prefetchable_hwtcl |
1 |
pf3_vf_bar2_prefetchable_hwtcl |
1 |
pf3_vf_bar3_prefetchable_hwtcl |
1 |
pf3_vf_bar4_prefetchable_hwtcl |
1 |
pf3_vf_bar5_prefetchable_hwtcl |
1 |
pf3_vf_bar0_size_hwtcl |
12 |
pf3_vf_bar1_size_hwtcl |
12 |
pf3_vf_bar2_size_hwtcl |
12 |
pf3_vf_bar3_size_hwtcl |
12 |
pf3_vf_bar4_size_hwtcl |
12 |
pf3_vf_bar5_size_hwtcl |
12 |
pf1_vendor_id_hwtcl |
0 |
pf1_device_id_hwtcl |
0 |
pf1_vf_device_id_hwtcl |
0 |
pf1_revision_id_hwtcl |
0 |
pf1_class_code_hwtcl |
0 |
pf1_subclass_code_hwtcl |
0 |
pf1_pci_prog_intfc_byte_hwtcl |
0 |
pf1_subsystem_vendor_id_hwtcl |
0 |
pf1_subsystem_device_id_hwtcl |
0 |
pf2_vendor_id_hwtcl |
0 |
pf2_device_id_hwtcl |
0 |
pf2_vf_device_id_hwtcl |
0 |
pf2_revision_id_hwtcl |
0 |
pf2_class_code_hwtcl |
0 |
pf2_subclass_code_hwtcl |
0 |
pf2_pci_prog_intfc_byte_hwtcl |
0 |
pf2_subsystem_vendor_id_hwtcl |
0 |
pf2_subsystem_device_id_hwtcl |
0 |
pf3_vendor_id_hwtcl |
0 |
pf3_device_id_hwtcl |
0 |
pf3_vf_device_id_hwtcl |
0 |
pf3_revision_id_hwtcl |
0 |
pf3_class_code_hwtcl |
0 |
pf3_subclass_code_hwtcl |
0 |
pf3_pci_prog_intfc_byte_hwtcl |
0 |
pf3_subsystem_vendor_id_hwtcl |
0 |
pf3_subsystem_device_id_hwtcl |
0 |
pf_msi_support_hwtcl |
0 |
pf0_msi_multi_message_capable_hwtcl |
4 |
pf1_msi_multi_message_capable_hwtcl |
4 |
pf2_msi_multi_message_capable_hwtcl |
4 |
pf3_msi_multi_message_capable_hwtcl |
4 |
pf_enable_function_msix_support_hwtcl |
0 |
vf_msix_cap_present_hwtcl |
0 |
pf0_msix_table_size_hwtcl |
0 |
pf0_msix_table_offset_hwtcl |
0 |
pf0_msix_table_bir_hwtcl |
0 |
pf0_msix_pba_offset_hwtcl |
0 |
pf0_msix_pba_bir_hwtcl |
0 |
pf1_msix_table_size_hwtcl |
0 |
pf1_msix_table_offset_hwtcl |
0 |
pf1_msix_table_bir_hwtcl |
0 |
pf1_msix_pba_offset_hwtcl |
0 |
pf1_msix_pba_bir_hwtcl |
0 |
pf2_msix_table_size_hwtcl |
0 |
pf2_msix_table_offset_hwtcl |
0 |
pf2_msix_table_bir_hwtcl |
0 |
pf2_msix_pba_offset_hwtcl |
0 |
pf2_msix_pba_bir_hwtcl |
0 |
pf3_msix_table_size_hwtcl |
0 |
pf3_msix_table_offset_hwtcl |
0 |
pf3_msix_table_bir_hwtcl |
0 |
pf3_msix_pba_offset_hwtcl |
0 |
pf3_msix_pba_bir_hwtcl |
0 |
pf0_vf_msix_tbl_size_hwtcl |
0 |
pf0_vf_msix_tbl_offset_hwtcl |
0 |
pf0_vf_msix_tbl_bir_hwtcl |
0 |
pf0_vf_msix_pba_offset_hwtcl |
0 |
pf0_vf_msix_pba_bir_hwtcl |
0 |
pf1_vf_msix_tbl_size_hwtcl |
0 |
pf1_vf_msix_tbl_offset_hwtcl |
0 |
pf1_vf_msix_tbl_bir_hwtcl |
0 |
pf1_vf_msix_pba_offset_hwtcl |
0 |
pf1_vf_msix_pba_bir_hwtcl |
0 |
pf2_vf_msix_tbl_size_hwtcl |
0 |
pf2_vf_msix_tbl_offset_hwtcl |
0 |
pf2_vf_msix_tbl_bir_hwtcl |
0 |
pf2_vf_msix_pba_offset_hwtcl |
0 |
pf2_vf_msix_pba_bir_hwtcl |
0 |
pf3_vf_msix_tbl_size_hwtcl |
0 |
pf3_vf_msix_tbl_offset_hwtcl |
0 |
pf3_vf_msix_tbl_bir_hwtcl |
0 |
pf3_vf_msix_pba_offset_hwtcl |
0 |
pf3_vf_msix_pba_bir_hwtcl |
0 |
pf0_interrupt_pin_hwtcl |
inta |
pf1_interrupt_pin_hwtcl |
inta |
pf2_interrupt_pin_hwtcl |
inta |
pf3_interrupt_pin_hwtcl |
inta |
pf0_intr_line_hwtcl |
0 |
pf1_intr_line_hwtcl |
0 |
pf2_intr_line_hwtcl |
0 |
pf3_intr_line_hwtcl |
0 |
app_msi_addr_pf_hwtcl |
64 |
app_msi_data_pf_hwtcl |
16 |
app_msi_mask_pf_hwtcl |
32 |
app_msi_msg_en_pf_hwtcl |
3 |
link2csr_width_hwtcl |
16 |
lmi_width_hwtcl |
8 |
cseb_route_to_avl_rx_st_hwtcl |
0 |
test_cseb_switch_hwtcl |
0 |
cseb_temp_busy_crs_hwtcl |
0 |
message_level |
error |
rx_polinv_soft_logic_enable |
0 |
enable_soft_dfe |
0 |
enable_gen3phase2eq_timechange |
0 |
gen3_coeff_3_ber_meas_hwtcl |
12ms |
slave_address_map_0_hwtcl |
32 |
slave_address_map_1_hwtcl |
0 |
slave_address_map_2_hwtcl |
0 |
slave_address_map_2_hprxm_hwtcl |
0 |
slave_address_map_3_hwtcl |
0 |
slave_address_map_4_hwtcl |
0 |
slave_address_map_5_hwtcl |
0 |
design_environment_hwtcl |
QSYS |
tlp_inspector_hwtcl |
0 |
tlp_inspector_use_signal_probe_hwtcl |
0 |
tlp_inspector_use_thin_rx_master |
0 |
tlp_insp_trg_dw0_hwtcl |
2049 |
tlp_insp_trg_dw1_hwtcl |
0 |
tlp_insp_trg_dw2_hwtcl |
0 |
enable_ast_trs_hwtcl |
0 |
ast_trs_num_desc_hwtcl |
16 |
ast_trs_txdata_width_hwtcl |
256 |
ast_trs_txdesc_width_hwtcl |
256 |
ast_trs_txstatus_width_hwtcl |
256 |
ast_trs_rxdata_width_hwtcl |
256 |
ast_trs_rxdesc_width_hwtcl |
256 |
ast_trs_txmty_width_hwtcl |
32 |
ast_trs_rxmty_width_hwtcl |
32 |
dma_use_scfifo_ext_hwtcl |
0 |
use_dynamic_design_example_hwtcl |
1 |
use_rpbfm_pro |
0 |
silicon_rev |
20nm5es |
hip_ac_pwr_clk_freq_in_hz |
125000000 |
ko_compl_data |
440 |
ko_compl_header |
112 |
acknack_base |
0 |
acknack_set |
false |
advance_error_reporting |
enable |
app_interface_width |
avst_128bit |
arb_upfc_30us_counter |
0 |
arb_upfc_30us_en |
enable |
aspm_config_management |
true |
aspm_patch_disable |
enable_both |
ast_width_rx |
rx_128 |
ast_width_tx |
tx_128 |
atomic_malformed |
false |
atomic_op_completer_32bit |
false |
atomic_op_completer_64bit |
false |
atomic_op_routing |
false |
auto_msg_drop_enable |
false |
bar0_size_mask |
0 |
bar0_type |
bar0_64bit_prefetch_mem |
bar1_size_mask |
0 |
bar1_type |
bar1_disable |
bar2_size_mask |
0 |
bar2_type |
bar2_disable |
bar3_size_mask |
0 |
bar3_type |
bar3_disable |
bar4_size_mask |
0 |
bar4_type |
bar4_disable |
bar5_size_mask |
0 |
bar5_type |
bar5_disable |
base_counter_sel |
count_clk_62p5 |
bist_memory_settings |
2417851639246850506078208 |
bridge_port_ssid_support |
false |
bridge_port_vga_enable |
false |
bypass_cdc |
false |
bypass_clk_switch |
false |
bypass_tl |
false |
cas_completer_128bit |
false |
cdc_clk_relation |
plesiochronous |
cdc_dummy_insert_limit |
11 |
cfg_parchk_ena |
disable |
cfgbp_req_recov_disable |
false |
class_code |
394240 |
clock_pwr_management |
false |
completion_timeout |
abcd |
core_clk_divider |
div_2 |
core_clk_freq_mhz |
core_clk_250mhz |
core_clk_out_sel |
core_clk_out_div_1 |
core_clk_sel |
pld_clk |
core_clk_source |
pll_fixed_clk |
cseb_bar_match_checking |
enable |
cseb_config_bypass |
disable |
cseb_cpl_status_during_cvp |
config_retry_status |
cseb_cpl_tag_checking |
enable |
cseb_disable_auto_crs |
false |
cseb_extend_pci |
false |
cseb_extend_pcie |
false |
cseb_min_error_checking |
false |
cseb_route_to_avl_rx_st |
cseb |
cseb_temp_busy_crs |
completer_abort_tmp_busy |
cvp_clk_reset |
false |
cvp_data_compressed |
false |
cvp_data_encrypted |
false |
cvp_enable |
cvp_dis |
cvp_mode_reset |
false |
cvp_rate_sel |
full_rate |
d0_pme |
true |
d1_pme |
false |
d1_support |
false |
d2_pme |
false |
d2_support |
false |
d3_cold_pme |
true |
d3_hot_pme |
true |
data_pack_rx |
disable |
deemphasis_enable |
false |
deskew_comma |
skp_eieos_deskw |
device_id |
57344 |
device_number |
0 |
device_specific_init |
false |
dft_clock_obsrv_en |
disable |
dft_clock_obsrv_sel |
dft_pclk |
diffclock_nfts_count |
128 |
dis_cplovf |
disable |
dis_paritychk |
disable |
disable_link_x2_support |
false |
disable_snoop_packet |
false |
dl_tx_check_parity_edb |
disable |
dll_active_report_support |
false |
early_dl_up |
false |
ecrc_check_capable |
false |
ecrc_gen_capable |
false |
egress_block_err_report_ena |
false |
ei_delay_powerdown_count |
10 |
eie_before_nfts_count |
4 |
electromech_interlock |
false |
en_ieiupdatefc |
false |
en_lane_errchk |
false |
en_phystatus_dly |
false |
ena_ido_cpl |
false |
ena_ido_req |
false |
enable_adapter_half_rate_mode |
false |
enable_ch0_pclk_out |
pclk_central |
enable_ch01_pclk_out |
pclk_ch0 |
enable_completion_timeout_disable |
true |
enable_directed_spd_chng |
false |
enable_function_msix_support |
false |
enable_l0s_aspm |
false |
enable_l1_aspm |
false |
enable_rx_buffer_checking |
false |
enable_rx_reordering |
true |
enable_slot_register |
false |
endpoint_l0_latency |
0 |
endpoint_l1_latency |
0 |
eql_rq_int_en_number |
0 |
errmgt_fcpe_patch_dis |
enable |
errmgt_fep_patch_dis |
enable |
expansion_base_address_register |
0 |
extend_tag_field |
false |
extended_format_field |
true |
extended_tag_reset |
false |
fc_init_timer |
1024 |
flow_control_timeout_count |
200 |
flow_control_update_count |
30 |
flr_capability |
false |
force_dis_to_det |
false |
force_gen1_dis |
false |
force_tx_coeff_preset_lpbk |
false |
frame_err_patch_dis |
enable |
func_mode |
enable |
g3_bypass_equlz |
false |
g3_coeff_done_tmout |
enable |
g3_deskew_char |
default_sdsos |
g3_dis_be_frm_err |
false |
g3_dn_rx_hint_eqlz_0 |
0 |
g3_dn_rx_hint_eqlz_1 |
0 |
g3_dn_rx_hint_eqlz_2 |
0 |
g3_dn_rx_hint_eqlz_3 |
0 |
g3_dn_rx_hint_eqlz_4 |
0 |
g3_dn_rx_hint_eqlz_5 |
0 |
g3_dn_rx_hint_eqlz_6 |
0 |
g3_dn_rx_hint_eqlz_7 |
0 |
g3_dn_tx_preset_eqlz_0 |
0 |
g3_dn_tx_preset_eqlz_1 |
0 |
g3_dn_tx_preset_eqlz_2 |
0 |
g3_dn_tx_preset_eqlz_3 |
0 |
g3_dn_tx_preset_eqlz_4 |
0 |
g3_dn_tx_preset_eqlz_5 |
0 |
g3_dn_tx_preset_eqlz_6 |
0 |
g3_dn_tx_preset_eqlz_7 |
0 |
g3_force_ber_max |
false |
g3_force_ber_min |
true |
g3_lnk_trn_rx_ts |
false |
g3_ltssm_eq_dbg |
false |
g3_ltssm_rec_dbg |
true |
g3_pause_ltssm_rec_en |
disable |
g3_quiesce_guarant |
false |
g3_redo_equlz_dis |
false |
g3_redo_equlz_en |
false |
g3_up_rx_hint_eqlz_0 |
0 |
g3_up_rx_hint_eqlz_1 |
0 |
g3_up_rx_hint_eqlz_2 |
0 |
g3_up_rx_hint_eqlz_3 |
0 |
g3_up_rx_hint_eqlz_4 |
0 |
g3_up_rx_hint_eqlz_5 |
0 |
g3_up_rx_hint_eqlz_6 |
0 |
g3_up_rx_hint_eqlz_7 |
0 |
g3_up_tx_preset_eqlz_0 |
0 |
g3_up_tx_preset_eqlz_1 |
0 |
g3_up_tx_preset_eqlz_2 |
0 |
g3_up_tx_preset_eqlz_3 |
0 |
g3_up_tx_preset_eqlz_4 |
0 |
g3_up_tx_preset_eqlz_5 |
0 |
g3_up_tx_preset_eqlz_6 |
0 |
g3_up_tx_preset_eqlz_7 |
0 |
gen123_lane_rate_mode |
gen1_gen2 |
gen2_diffclock_nfts_count |
255 |
gen2_pma_pll_usage |
use_ffpll |
gen2_sameclock_nfts_count |
255 |
gen3_coeff_1 |
8 |
gen3_coeff_1_ber_meas |
4 |
gen3_coeff_1_nxtber_less |
1 |
gen3_coeff_1_nxtber_more |
1 |
gen3_coeff_1_preset_hint |
0 |
gen3_coeff_1_reqber |
0 |
gen3_coeff_1_sel |
preset_1 |
gen3_coeff_10 |
0 |
gen3_coeff_10_ber_meas |
0 |
gen3_coeff_10_nxtber_less |
0 |
gen3_coeff_10_nxtber_more |
0 |
gen3_coeff_10_preset_hint |
0 |
gen3_coeff_10_reqber |
0 |
gen3_coeff_10_sel |
preset_10 |
gen3_coeff_11 |
0 |
gen3_coeff_11_ber_meas |
0 |
gen3_coeff_11_nxtber_less |
0 |
gen3_coeff_11_nxtber_more |
0 |
gen3_coeff_11_preset_hint |
0 |
gen3_coeff_11_reqber |
0 |
gen3_coeff_11_sel |
preset_11 |
gen3_coeff_12 |
0 |
gen3_coeff_12_ber_meas |
0 |
gen3_coeff_12_nxtber_less |
0 |
gen3_coeff_12_nxtber_more |
0 |
gen3_coeff_12_preset_hint |
0 |
gen3_coeff_12_reqber |
0 |
gen3_coeff_12_sel |
preset_12 |
gen3_coeff_13 |
0 |
gen3_coeff_13_ber_meas |
0 |
gen3_coeff_13_nxtber_less |
0 |
gen3_coeff_13_nxtber_more |
0 |
gen3_coeff_13_preset_hint |
0 |
gen3_coeff_13_reqber |
0 |
gen3_coeff_13_sel |
preset_13 |
gen3_coeff_14 |
0 |
gen3_coeff_14_ber_meas |
0 |
gen3_coeff_14_nxtber_less |
0 |
gen3_coeff_14_nxtber_more |
0 |
gen3_coeff_14_preset_hint |
0 |
gen3_coeff_14_reqber |
0 |
gen3_coeff_14_sel |
preset_14 |
gen3_coeff_15 |
0 |
gen3_coeff_15_ber_meas |
0 |
gen3_coeff_15_nxtber_less |
0 |
gen3_coeff_15_nxtber_more |
0 |
gen3_coeff_15_preset_hint |
0 |
gen3_coeff_15_reqber |
0 |
gen3_coeff_15_sel |
preset_15 |
gen3_coeff_16 |
0 |
gen3_coeff_16_ber_meas |
0 |
gen3_coeff_16_nxtber_less |
0 |
gen3_coeff_16_nxtber_more |
0 |
gen3_coeff_16_preset_hint |
0 |
gen3_coeff_16_reqber |
0 |
gen3_coeff_16_sel |
preset_16 |
gen3_coeff_17 |
196608 |
gen3_coeff_17_ber_meas |
0 |
gen3_coeff_17_nxtber_less |
0 |
gen3_coeff_17_nxtber_more |
0 |
gen3_coeff_17_preset_hint |
0 |
gen3_coeff_17_reqber |
0 |
gen3_coeff_17_sel |
preset_17 |
gen3_coeff_18 |
196609 |
gen3_coeff_18_ber_meas |
0 |
gen3_coeff_18_nxtber_less |
0 |
gen3_coeff_18_nxtber_more |
0 |
gen3_coeff_18_preset_hint |
0 |
gen3_coeff_18_reqber |
0 |
gen3_coeff_18_sel |
preset_18 |
gen3_coeff_19 |
196609 |
gen3_coeff_19_ber_meas |
0 |
gen3_coeff_19_nxtber_less |
0 |
gen3_coeff_19_nxtber_more |
0 |
gen3_coeff_19_preset_hint |
0 |
gen3_coeff_19_reqber |
0 |
gen3_coeff_19_sel |
preset_19 |
gen3_coeff_2 |
8 |
gen3_coeff_2_ber_meas |
4 |
gen3_coeff_2_nxtber_less |
2 |
gen3_coeff_2_nxtber_more |
2 |
gen3_coeff_2_preset_hint |
7 |
gen3_coeff_2_reqber |
0 |
gen3_coeff_2_sel |
preset_2 |
gen3_coeff_20 |
196609 |
gen3_coeff_20_ber_meas |
0 |
gen3_coeff_20_nxtber_less |
0 |
gen3_coeff_20_nxtber_more |
0 |
gen3_coeff_20_preset_hint |
0 |
gen3_coeff_20_reqber |
0 |
gen3_coeff_20_sel |
preset_20 |
gen3_coeff_21 |
196609 |
gen3_coeff_21_ber_meas |
0 |
gen3_coeff_21_nxtber_less |
0 |
gen3_coeff_21_nxtber_more |
0 |
gen3_coeff_21_preset_hint |
0 |
gen3_coeff_21_reqber |
0 |
gen3_coeff_21_sel |
preset_21 |
gen3_coeff_22 |
196609 |
gen3_coeff_22_ber_meas |
0 |
gen3_coeff_22_nxtber_less |
7 |
gen3_coeff_22_nxtber_more |
0 |
gen3_coeff_22_preset_hint |
0 |
gen3_coeff_22_reqber |
0 |
gen3_coeff_22_sel |
preset_22 |
gen3_coeff_23 |
196609 |
gen3_coeff_23_ber_meas |
0 |
gen3_coeff_23_nxtber_less |
0 |
gen3_coeff_23_nxtber_more |
0 |
gen3_coeff_23_preset_hint |
0 |
gen3_coeff_23_reqber |
0 |
gen3_coeff_23_sel |
preset_23 |
gen3_coeff_24 |
196609 |
gen3_coeff_24_ber_meas |
0 |
gen3_coeff_24_nxtber_less |
0 |
gen3_coeff_24_nxtber_more |
0 |
gen3_coeff_24_preset_hint |
7 |
gen3_coeff_24_reqber |
0 |
gen3_coeff_24_sel |
preset_24 |
gen3_coeff_3 |
8 |
gen3_coeff_3_ber_meas |
16 |
gen3_coeff_3_nxtber_less |
4 |
gen3_coeff_3_nxtber_more |
4 |
gen3_coeff_3_preset_hint |
7 |
gen3_coeff_3_reqber |
31 |
gen3_coeff_3_sel |
preset_3 |
gen3_coeff_4 |
8 |
gen3_coeff_4_ber_meas |
4 |
gen3_coeff_4_nxtber_less |
4 |
gen3_coeff_4_nxtber_more |
4 |
gen3_coeff_4_preset_hint |
7 |
gen3_coeff_4_reqber |
31 |
gen3_coeff_4_sel |
preset_4 |
gen3_coeff_5 |
0 |
gen3_coeff_5_ber_meas |
0 |
gen3_coeff_5_nxtber_less |
0 |
gen3_coeff_5_nxtber_more |
0 |
gen3_coeff_5_preset_hint |
7 |
gen3_coeff_5_reqber |
0 |
gen3_coeff_5_sel |
preset_5 |
gen3_coeff_6 |
0 |
gen3_coeff_6_ber_meas |
0 |
gen3_coeff_6_nxtber_less |
0 |
gen3_coeff_6_nxtber_more |
0 |
gen3_coeff_6_preset_hint |
0 |
gen3_coeff_6_reqber |
0 |
gen3_coeff_6_sel |
preset_6 |
gen3_coeff_7 |
0 |
gen3_coeff_7_ber_meas |
0 |
gen3_coeff_7_nxtber_less |
0 |
gen3_coeff_7_nxtber_more |
0 |
gen3_coeff_7_preset_hint |
0 |
gen3_coeff_7_reqber |
0 |
gen3_coeff_7_sel |
preset_7 |
gen3_coeff_8 |
0 |
gen3_coeff_8_ber_meas |
0 |
gen3_coeff_8_nxtber_less |
0 |
gen3_coeff_8_nxtber_more |
0 |
gen3_coeff_8_preset_hint |
0 |
gen3_coeff_8_reqber |
0 |
gen3_coeff_8_sel |
preset_8 |
gen3_coeff_9 |
0 |
gen3_coeff_9_ber_meas |
0 |
gen3_coeff_9_nxtber_less |
0 |
gen3_coeff_9_nxtber_more |
0 |
gen3_coeff_9_preset_hint |
0 |
gen3_coeff_9_reqber |
0 |
gen3_coeff_9_sel |
preset_9 |
gen3_coeff_delay_count |
125 |
gen3_coeff_errchk |
disable |
gen3_dcbal_en |
true |
gen3_diffclock_nfts_count |
128 |
gen3_force_local_coeff |
false |
gen3_full_swing |
60 |
gen3_half_swing |
false |
gen3_low_freq |
20 |
gen3_paritychk |
disable |
gen3_pl_framing_err_dis |
enable |
gen3_preset_coeff_1 |
64320 |
gen3_preset_coeff_10 |
3210 |
gen3_preset_coeff_11 |
84480 |
gen3_preset_coeff_2 |
44160 |
gen3_preset_coeff_3 |
52224 |
gen3_preset_coeff_4 |
36096 |
gen3_preset_coeff_5 |
3840 |
gen3_preset_coeff_6 |
3462 |
gen3_preset_coeff_7 |
3336 |
gen3_preset_coeff_8 |
51846 |
gen3_preset_coeff_9 |
35592 |
gen3_reset_eieos_cnt_bit |
false |
gen3_rxfreqlock_counter |
0 |
gen3_sameclock_nfts_count |
128 |
gen3_scrdscr_bypass |
true |
gen3_skip_ph2_ph3 |
false |
hard_reset_bypass |
false |
hard_rst_sig_chnl_en |
enable_hrc_sig_x8 |
hard_rst_tx_pll_rst_chnl_en |
enable_hrc_txpll_rst_ch4 |
hip_base_address |
0 |
hip_clock_dis |
enable_hip_clk |
hip_hard_reset |
enable |
hip_pcs_sig_chnl_en |
enable_hip_pcs_sig_x8 |
hot_plug_support |
0 |
hrc_chnl_txpll_master_cgb_rst_select |
ch3_master_cgb_sel |
hrdrstctrl_en |
hrdrstctrl_en |
iei_enable_settings |
gen3_infei_infsd_gen2_infsd_gen1_infsd_sd |
indicator |
0 |
intel_id_access |
false |
interrupt_pin |
inta |
io_window_addr_width |
none |
jtag_id |
0 |
l0_exit_latency_diffclock |
6 |
l0_exit_latency_sameclock |
6 |
l01_entry_latency |
31 |
l0s_adj_rply_timer_dis |
enable |
l1_exit_latency_diffclock |
0 |
l1_exit_latency_sameclock |
0 |
l2_async_logic |
disable |
lane_mask |
ln_mask_x8 |
lane_rate |
gen2 |
link_width |
x8 |
low_priority_vc |
single_vc_low_pr |
ltr_mechanism |
false |
ltssm_1ms_timeout |
disable |
ltssm_freqlocked_check |
disable |
malformed_tlp_truncate_en |
disable |
max_link_width |
x8_link_width |
max_payload_size |
payload_256 |
maximum_current |
0 |
millisecond_cycle_count |
248496 |
msi_64bit_addressing_capable |
true |
msi_masking_capable |
false |
msi_multi_message_capable |
count_4 |
msi_support |
true |
msix_pba_bir |
0 |
msix_pba_offset |
0 |
msix_table_bir |
0 |
msix_table_offset |
0 |
msix_table_size |
0 |
national_inst_thru_enhance |
false |
no_command_completed |
false |
no_soft_reset |
false |
pcie_base_spec |
pcie_3p0 |
pcie_mode |
rp |
pcie_spec_1p0_compliance |
spec_1p1 |
pcie_spec_version |
v3 |
pclk_out_sel |
pclk |
pld_in_use_reg |
false |
pm_latency_patch_dis |
enable |
pm_txdl_patch_dis |
enable |
pme_clock |
false |
port_link_number |
1 |
port_type |
root_port |
powerdown_mode |
powerup |
prefetchable_mem_window_addr_width |
prefetch_0 |
r2c_mask_easy |
false |
r2c_mask_enable |
false |
rec_frqlk_mon_en |
disable |
register_pipe_signals |
true |
retry_buffer_last_active_address |
1023 |
retry_buffer_memory_settings |
12885005388 |
retry_ecc_corr_mask_dis |
enable |
revision_id |
1 |
role_based_error_reporting |
true |
rp_bug_fix_pri_sec_stat_reg |
127 |
rpltim_base |
16 |
rpltim_set |
true |
rstctl_ltssm_dis |
false |
rstctrl_1ms_count_fref_clk |
100000 |
rstctrl_1us_count_fref_clk |
100 |
rstctrl_altpe3_crst_n_inv |
false |
rstctrl_altpe3_rst_n_inv |
false |
rstctrl_altpe3_srst_n_inv |
false |
rstctrl_chnl_cal_done_select |
ch01234567_out_chnl_cal_done |
rstctrl_debug_en |
false |
rstctrl_force_inactive_rst |
false |
rstctrl_fref_clk_select |
ch0_sel |
rstctrl_hard_block_enable |
hard_rst_ctl |
rstctrl_hip_ep |
hip_not_ep |
rstctrl_mask_tx_pll_lock_select |
ch3_sel_mask_tx_pll_lock |
rstctrl_perst_enable |
level |
rstctrl_perstn_select |
perstn_pin |
rstctrl_pld_clr |
true |
rstctrl_pll_cal_done_select |
ch4_sel_pll_cal_done |
rstctrl_rx_pcs_rst_n_inv |
false |
rstctrl_rx_pcs_rst_n_select |
ch01234567_out_rx_pcs_rst |
rstctrl_rx_pll_freq_lock_select |
not_active_rx_pll_f_lock |
rstctrl_rx_pll_lock_select |
ch01234567_sel_rx_pll_lock |
rstctrl_rx_pma_rstb_inv |
false |
rstctrl_rx_pma_rstb_select |
ch01234567_out_rx_pma_rstb |
rstctrl_timer_a |
10 |
rstctrl_timer_a_type |
a_timer_fref_cycles |
rstctrl_timer_b |
10 |
rstctrl_timer_b_type |
b_timer_fref_cycles |
rstctrl_timer_c |
10 |
rstctrl_timer_c_type |
c_timer_fref_cycles |
rstctrl_timer_d |
20 |
rstctrl_timer_d_type |
d_timer_fref_cycles |
rstctrl_timer_e |
1 |
rstctrl_timer_e_type |
e_timer_fref_cycles |
rstctrl_timer_f |
10 |
rstctrl_timer_f_type |
f_timer_fref_cycles |
rstctrl_timer_g |
10 |
rstctrl_timer_g_type |
g_timer_fref_cycles |
rstctrl_timer_h |
4 |
rstctrl_timer_h_type |
h_timer_micro_secs |
rstctrl_timer_i |
20 |
rstctrl_timer_i_type |
i_timer_fref_cycles |
rstctrl_timer_j |
20 |
rstctrl_timer_j_type |
j_timer_fref_cycles |
rstctrl_tx_lcff_pll_lock_select |
ch4_sel_lcff_pll_lock |
rstctrl_tx_lcff_pll_rstb_select |
ch4_out_lcff_pll_rstb |
rstctrl_tx_pcs_rst_n_inv |
false |
rstctrl_tx_pcs_rst_n_select |
ch01234567_out_tx_pcs_rst |
rstctrl_tx_pma_rstb_inv |
false |
rstctrl_tx_pma_syncp_inv |
false |
rstctrl_tx_pma_syncp_select |
ch3_out_tx_pma_syncp |
rx_ast_parity |
disable |
rx_buffer_credit_alloc |
balance |
rx_buffer_fc_protect |
68 |
rx_buffer_protect |
68 |
rx_cdc_almost_empty |
3 |
rx_cdc_almost_full |
12 |
rx_cred_ctl_param |
disable |
rx_ei_l0s |
disable |
rx_l0s_count_idl |
0 |
rx_ptr0_nonposted_dpram_max |
2047 |
rx_ptr0_nonposted_dpram_min |
1928 |
rx_ptr0_posted_dpram_max |
1927 |
rx_ptr0_posted_dpram_min |
0 |
rx_runt_patch_dis |
enable |
rx_sop_ctrl |
rx_sop_boundary_128 |
rx_trunc_patch_dis |
enable |
rx_use_prst |
true |
rx_use_prst_ep |
false |
rxbuf_ecc_corr_mask_dis |
enable |
sameclock_nfts_count |
128 |
sel_enable_pcs_rx_fifo_err |
disable_sel |
sim_mode |
disable |
simple_ro_fifo_control_en |
disable |
single_rx_detect |
detect_all_lanes |
skp_os_gen3_count |
0 |
skp_os_schedule_count |
0 |
slot_number |
0 |
slot_power_limit |
0 |
slot_power_scale |
0 |
slotclk_cfg |
static_slotclkcfgon |
ssid |
0 |
ssvid |
0 |
subsystem_device_id |
57344 |
subsystem_vendor_id |
4466 |
sup_mode |
user_mode |
surprise_down_error_support |
false |
tl_cfg_div |
cfg_clk_div_7 |
tl_tx_check_parity_msg |
disable |
tph_completer |
false |
tx_ast_parity |
disable |
tx_cdc_almost_empty |
5 |
tx_cdc_almost_full |
11 |
tx_sop_ctrl |
boundary_128 |
tx_swing |
0 |
txdl_fair_arbiter_counter |
0 |
txdl_fair_arbiter_en |
enable |
txrate_adv |
capability |
uc_calibration_en |
uc_calibration_en |
use_aer |
true |
use_crc_forwarding |
false |
user_id |
0 |
vc_arbitration |
single_vc_arb |
vc_enable |
single_vc |
vc0_clk_enable |
true |
vc0_rx_buffer_memory_settings |
12885005388 |
vc0_rx_flow_ctrl_compl_data |
0 |
vc0_rx_flow_ctrl_compl_header |
0 |
vc0_rx_flow_ctrl_nonposted_data |
0 |
vc0_rx_flow_ctrl_nonposted_header |
56 |
vc0_rx_flow_ctrl_posted_data |
358 |
vc0_rx_flow_ctrl_posted_header |
50 |
vc1_clk_enable |
false |
vendor_id |
4466 |
vsec_cap |
0 |
vsec_id |
4466 |
wrong_device_id |
disable |
not_use_k_gbl_bits |
not_used_k_gbl |
avmm_force_inter_sel_csr_ctrl |
disable |
operating_voltage |
standard |
rxdl_bad_tlp_patch_dis |
rxdlbug2_enable_both |
avmm_dprio_broadcast_en_csr_ctrl |
disable |
hip_ac_pwr_uw_per_mhz |
1120 |
rxdl_bad_sop_eop_filter_dis |
rxdlbug1_enable_both |
rxdl_lcrc_patch_dis |
rxdlbug3_enable_both |
capab_rate_rxcfg_en |
disable |
avmm_cvp_inter_sel_csr_ctrl |
disable |
lmi_hold_off_cfg_timer_en |
disable |
avmm_power_iso_en_csr_ctrl |
disable |
AUTO_RXM_IRQ_INTERRUPTS_USED |
0 |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |