interface_type_hwtcl |
Avalon-MM |
wrala_hwtcl |
7 |
avmm_addr_width_hwtcl |
32 |
cb_pcie_mode_hwtcl |
0 |
cb_pcie_rx_lite_hwtcl |
0 |
cg_impl_cra_av_slave_port_hwtcl |
1 |
cg_enable_advanced_interrupt_hwtcl |
0 |
cg_enable_a2p_interrupt_hwtcl |
0 |
enable_hip_status_for_avmm_hwtcl |
1 |
cg_a2p_addr_map_num_entries_hwtcl |
2 |
cg_a2p_addr_map_pass_thru_bits_hwtcl |
27 |
port_type_hwtcl |
Root port |
rx_buffer_credit_alloc_hwtcl |
Balanced |
rx_buffer_credit_alloc_display |
Header:112 Data:440 |
enable_avst_reset_hwtcl |
1 |
use_ast_parity_hwtcl |
0 |
multiple_packets_per_cycle_hwtcl |
0 |
cvp_enable_hwtcl |
0 |
use_tx_cons_cred_sel_hwtcl |
0 |
hip_reconfig_hwtcl |
0 |
xcvr_reconfig_hwtcl |
0 |
adme_enable_hwtcl |
1 |
enable_devkit_conduit_hwtcl |
0 |
select_design_example_hwtcl |
PIO |
enable_example_design_sim_hwtcl |
1 |
enable_example_design_synth_hwtcl |
1 |
select_design_example_rtl_lang_hwtcl |
Verilog |
targeted_devkit_hwtcl |
Arria 10 GX FPGA Development Kit |
bar0_type_hwtcl |
64-bit prefetchable memory |
bar1_type_hwtcl |
Disabled |
bar2_type_hwtcl |
Disabled |
bar3_type_hwtcl |
Disabled |
bar4_type_hwtcl |
Disabled |
bar5_type_hwtcl |
Disabled |
bar0_address_width_avmm_hwtcl |
32 |
bar1_address_width_avmm_hwtcl |
0 |
bar2_address_width_avmm_hwtcl |
0 |
bar3_address_width_avmm_hwtcl |
0 |
bar4_address_width_avmm_hwtcl |
0 |
bar5_address_width_avmm_hwtcl |
0 |
io_window_addr_width_hwtcl |
0 |
prefetchable_mem_window_addr_width_hwtcl |
0 |
vendor_id_hwtcl |
4466 |
device_id_hwtcl |
57344 |
revision_id_hwtcl |
1 |
class_code_hwtcl |
394240 |
subsystem_vendor_id_hwtcl |
4466 |
subsystem_device_id_hwtcl |
57344 |
maximum_payload_size_hwtcl |
256 |
completion_timeout_hwtcl |
ABCD |
completion_timeout_disable_hwtcl |
1 |
advance_error_reporting_hwtcl |
1 |
ecrc_check_capable_hwtcl |
0 |
ecrc_gen_capable_hwtcl |
0 |
use_crc_forwarding_hwtcl |
0 |
track_rxfc_cplbuf_ovf_hwtcl |
0 |
port_link_number_hwtcl |
1 |
dll_active_report_support_hwtcl |
0 |
surprise_down_error_support_hwtcl |
0 |
slot_clock_cfg_hwtcl |
1 |
msi_multi_message_capable_hwtcl |
4 |
vsec_id_hwtcl |
4466 |
vsec_cap_hwtcl |
0 |
user_id_hwtcl |
0 |
enable_function_msix_support_hwtcl |
0 |
msix_table_size_hwtcl |
0 |
msix_table_offset_hwtcl |
0 |
msix_table_bir_hwtcl |
0 |
msix_pba_offset_hwtcl |
0 |
msix_pba_bir_hwtcl |
0 |
enable_slot_register_hwtcl |
0 |
slot_power_scale_hwtcl |
0 |
slot_power_limit_hwtcl |
0 |
slot_number_hwtcl |
0 |
endpoint_l0_latency_hwtcl |
0 |
endpoint_l1_latency_hwtcl |
0 |
deemphasis_enable_hwtcl |
0 |
gen3_coeff_1_hwtcl |
8 |
pf0_virtio_capability_present_hwtcl |
0 |
pf0_virtio_device_specific_cap_present_hwtcl |
0 |
pf0_virtio_cmn_config_bar_indicator_hwtcl |
0 |
pf0_virtio_cmn_config_bar_offset_hwtcl |
0 |
pf0_virtio_cmn_config_structure_length_hwtcl |
0 |
pf0_virtio_notification_bar_indicator_hwtcl |
0 |
pf0_virtio_notification_bar_offset_hwtcl |
0 |
pf0_virtio_notification_structure_length_hwtcl |
0 |
pf0_virtio_isrstatus_bar_indicator_hwtcl |
0 |
pf0_virtio_isrstatus_bar_offset_hwtcl |
0 |
pf0_virtio_isrstatus_structure_length_hwtcl |
0 |
pf0_virtio_devspecific_bar_indicator_hwtcl |
0 |
pf0_virtio_devspecific_bar_offset_hwtcl |
0 |
pf0_virtio_devspecific_structure_length_hwtcl |
0 |
pf0_virtio_pciconfig_access_bar_indicator_hwtcl |
0 |
pf0_virtio_pciconfig_access_bar_offset_hwtcl |
0 |
pf0_virtio_pciconfig_access_structure_length_hwtcl |
0 |
pf1_virtio_capability_present_hwtcl |
0 |
pf1_virtio_device_specific_cap_present_hwtcl |
0 |
pf1_virtio_cmn_config_bar_indicator_hwtcl |
0 |
pf1_virtio_cmn_config_bar_offset_hwtcl |
0 |
pf1_virtio_cmn_config_structure_length_hwtcl |
0 |
pf1_virtio_notification_bar_indicator_hwtcl |
0 |
pf1_virtio_notification_bar_offset_hwtcl |
0 |
pf1_virtio_notification_structure_length_hwtcl |
0 |
pf1_virtio_isrstatus_bar_indicator_hwtcl |
0 |
pf1_virtio_isrstatus_bar_offset_hwtcl |
0 |
pf1_virtio_isrstatus_structure_length_hwtcl |
0 |
pf1_virtio_devspecific_bar_indicator_hwtcl |
0 |
pf1_virtio_devspecific_bar_offset_hwtcl |
0 |
pf1_virtio_devspecific_structure_length_hwtcl |
0 |
pf1_virtio_pciconfig_access_bar_indicator_hwtcl |
0 |
pf1_virtio_pciconfig_access_bar_offset_hwtcl |
0 |
pf1_virtio_pciconfig_access_structure_length_hwtcl |
0 |
pf2_virtio_capability_present_hwtcl |
0 |
pf2_virtio_device_specific_cap_present_hwtcl |
0 |
pf2_virtio_cmn_config_bar_indicator_hwtcl |
0 |
pf2_virtio_cmn_config_bar_offset_hwtcl |
0 |
pf2_virtio_cmn_config_structure_length_hwtcl |
0 |
pf2_virtio_notification_bar_indicator_hwtcl |
0 |
pf2_virtio_notification_bar_offset_hwtcl |
0 |
pf2_virtio_notification_structure_length_hwtcl |
0 |
pf2_virtio_isrstatus_bar_indicator_hwtcl |
0 |
pf2_virtio_isrstatus_bar_offset_hwtcl |
0 |
pf2_virtio_isrstatus_structure_length_hwtcl |
0 |
pf2_virtio_devspecific_bar_indicator_hwtcl |
0 |
pf2_virtio_devspecific_bar_offset_hwtcl |
0 |
pf2_virtio_devspecific_structure_length_hwtcl |
0 |
pf2_virtio_pciconfig_access_bar_indicator_hwtcl |
0 |
pf2_virtio_pciconfig_access_bar_offset_hwtcl |
0 |
pf2_virtio_pciconfig_access_structure_length_hwtcl |
0 |
pf3_virtio_capability_present_hwtcl |
0 |
pf3_virtio_device_specific_cap_present_hwtcl |
0 |
pf3_virtio_cmn_config_bar_indicator_hwtcl |
0 |
pf3_virtio_cmn_config_bar_offset_hwtcl |
0 |
pf3_virtio_cmn_config_structure_length_hwtcl |
0 |
pf3_virtio_notification_bar_indicator_hwtcl |
0 |
pf3_virtio_notification_bar_offset_hwtcl |
0 |
pf3_virtio_notification_structure_length_hwtcl |
0 |
pf3_virtio_isrstatus_bar_indicator_hwtcl |
0 |
pf3_virtio_isrstatus_bar_offset_hwtcl |
0 |
pf3_virtio_isrstatus_structure_length_hwtcl |
0 |
pf3_virtio_devspecific_bar_indicator_hwtcl |
0 |
pf3_virtio_devspecific_bar_offset_hwtcl |
0 |
pf3_virtio_devspecific_structure_length_hwtcl |
0 |
pf3_virtio_pciconfig_access_bar_indicator_hwtcl |
0 |
pf3_virtio_pciconfig_access_bar_offset_hwtcl |
0 |
pf3_virtio_pciconfig_access_structure_length_hwtcl |
0 |
pf4_virtio_capability_present_hwtcl |
0 |
pf4_virtio_device_specific_cap_present_hwtcl |
0 |
pf4_virtio_cmn_config_bar_indicator_hwtcl |
0 |
pf4_virtio_cmn_config_bar_offset_hwtcl |
0 |
pf4_virtio_cmn_config_structure_length_hwtcl |
0 |
pf4_virtio_notification_bar_indicator_hwtcl |
0 |
pf4_virtio_notification_bar_offset_hwtcl |
0 |
pf4_virtio_notification_structure_length_hwtcl |
0 |
pf4_virtio_isrstatus_bar_indicator_hwtcl |
0 |
pf4_virtio_isrstatus_bar_offset_hwtcl |
0 |
pf4_virtio_isrstatus_structure_length_hwtcl |
0 |
pf4_virtio_devspecific_bar_indicator_hwtcl |
0 |
pf4_virtio_devspecific_bar_offset_hwtcl |
0 |
pf4_virtio_devspecific_structure_length_hwtcl |
0 |
pf4_virtio_pciconfig_access_bar_indicator_hwtcl |
0 |
pf4_virtio_pciconfig_access_bar_offset_hwtcl |
0 |
pf4_virtio_pciconfig_access_structure_length_hwtcl |
0 |
pf5_virtio_capability_present_hwtcl |
0 |
pf5_virtio_device_specific_cap_present_hwtcl |
0 |
pf5_virtio_cmn_config_bar_indicator_hwtcl |
0 |
pf5_virtio_cmn_config_bar_offset_hwtcl |
0 |
pf5_virtio_cmn_config_structure_length_hwtcl |
0 |
pf5_virtio_notification_bar_indicator_hwtcl |
0 |
pf5_virtio_notification_bar_offset_hwtcl |
0 |
pf5_virtio_notification_structure_length_hwtcl |
0 |
pf5_virtio_isrstatus_bar_indicator_hwtcl |
0 |
pf5_virtio_isrstatus_bar_offset_hwtcl |
0 |
pf5_virtio_isrstatus_structure_length_hwtcl |
0 |
pf5_virtio_devspecific_bar_indicator_hwtcl |
0 |
pf5_virtio_devspecific_bar_offset_hwtcl |
0 |
pf5_virtio_devspecific_structure_length_hwtcl |
0 |
pf5_virtio_pciconfig_access_bar_indicator_hwtcl |
0 |
pf5_virtio_pciconfig_access_bar_offset_hwtcl |
0 |
pf5_virtio_pciconfig_access_structure_length_hwtcl |
0 |
pf6_virtio_capability_present_hwtcl |
0 |
pf6_virtio_device_specific_cap_present_hwtcl |
0 |
pf6_virtio_cmn_config_bar_indicator_hwtcl |
0 |
pf6_virtio_cmn_config_bar_offset_hwtcl |
0 |
pf6_virtio_cmn_config_structure_length_hwtcl |
0 |
pf6_virtio_notification_bar_indicator_hwtcl |
0 |
pf6_virtio_notification_bar_offset_hwtcl |
0 |
pf6_virtio_notification_structure_length_hwtcl |
0 |
pf6_virtio_isrstatus_bar_indicator_hwtcl |
0 |
pf6_virtio_isrstatus_bar_offset_hwtcl |
0 |
pf6_virtio_isrstatus_structure_length_hwtcl |
0 |
pf6_virtio_devspecific_bar_indicator_hwtcl |
0 |
pf6_virtio_devspecific_bar_offset_hwtcl |
0 |
pf6_virtio_devspecific_structure_length_hwtcl |
0 |
pf6_virtio_pciconfig_access_bar_indicator_hwtcl |
0 |
pf6_virtio_pciconfig_access_bar_offset_hwtcl |
0 |
pf6_virtio_pciconfig_access_structure_length_hwtcl |
0 |
pf7_virtio_capability_present_hwtcl |
0 |
pf7_virtio_device_specific_cap_present_hwtcl |
0 |
pf7_virtio_cmn_config_bar_indicator_hwtcl |
0 |
pf7_virtio_cmn_config_bar_offset_hwtcl |
0 |
pf7_virtio_cmn_config_structure_length_hwtcl |
0 |
pf7_virtio_notification_bar_indicator_hwtcl |
0 |
pf7_virtio_notification_bar_offset_hwtcl |
0 |
pf7_virtio_notification_structure_length_hwtcl |
0 |
pf7_virtio_isrstatus_bar_indicator_hwtcl |
0 |
pf7_virtio_isrstatus_bar_offset_hwtcl |
0 |
pf7_virtio_isrstatus_structure_length_hwtcl |
0 |
pf7_virtio_devspecific_bar_indicator_hwtcl |
0 |
pf7_virtio_devspecific_bar_offset_hwtcl |
0 |
pf7_virtio_devspecific_structure_length_hwtcl |
0 |
pf7_virtio_pciconfig_access_bar_indicator_hwtcl |
0 |
pf7_virtio_pciconfig_access_bar_offset_hwtcl |
0 |
pf7_virtio_pciconfig_access_structure_length_hwtcl |
0 |
pf0_msix_table_size_hwtcl |
0 |
pf0_msix_table_offset_hwtcl |
0 |
pf0_msix_table_bir_hwtcl |
0 |
pf0_msix_pba_offset_hwtcl |
0 |
pf0_msix_pba_bir_hwtcl |
0 |
pf1_msix_table_size_hwtcl |
0 |
pf1_msix_table_offset_hwtcl |
0 |
pf1_msix_table_bir_hwtcl |
0 |
pf1_msix_pba_offset_hwtcl |
0 |
pf1_msix_pba_bir_hwtcl |
0 |
pf2_msix_table_size_hwtcl |
0 |
pf2_msix_table_offset_hwtcl |
0 |
pf2_msix_table_bir_hwtcl |
0 |
pf2_msix_pba_offset_hwtcl |
0 |
pf2_msix_pba_bir_hwtcl |
0 |
pf3_msix_table_size_hwtcl |
0 |
pf3_msix_table_offset_hwtcl |
0 |
pf3_msix_table_bir_hwtcl |
0 |
pf3_msix_pba_offset_hwtcl |
0 |
pf3_msix_pba_bir_hwtcl |
0 |
pf4_msix_table_size_hwtcl |
0 |
pf4_msix_table_offset_hwtcl |
0 |
pf4_msix_table_bir_hwtcl |
0 |
pf4_msix_pba_offset_hwtcl |
0 |
pf4_msix_pba_bir_hwtcl |
0 |
pf5_msix_table_size_hwtcl |
0 |
pf5_msix_table_offset_hwtcl |
0 |
pf5_msix_table_bir_hwtcl |
0 |
pf5_msix_pba_offset_hwtcl |
0 |
pf5_msix_pba_bir_hwtcl |
0 |
pf6_msix_table_size_hwtcl |
0 |
pf6_msix_table_offset_hwtcl |
0 |
pf6_msix_table_bir_hwtcl |
0 |
pf6_msix_pba_offset_hwtcl |
0 |
pf6_msix_pba_bir_hwtcl |
0 |
pf7_msix_table_size_hwtcl |
0 |
pf7_msix_table_offset_hwtcl |
0 |
pf7_msix_table_bir_hwtcl |
0 |
pf7_msix_pba_offset_hwtcl |
0 |
pf7_msix_pba_bir_hwtcl |
0 |
pf0_vf_msix_tbl_size_hwtcl |
0 |
pf0_vf_msix_tbl_offset_hwtcl |
0 |
pf0_vf_msix_tbl_bir_hwtcl |
0 |
pf0_vf_msix_pba_offset_hwtcl |
0 |
pf0_vf_msix_pba_bir_hwtcl |
0 |
pf1_vf_msix_tbl_size_hwtcl |
0 |
pf1_vf_msix_tbl_offset_hwtcl |
0 |
pf1_vf_msix_tbl_bir_hwtcl |
0 |
pf1_vf_msix_pba_offset_hwtcl |
0 |
pf1_vf_msix_pba_bir_hwtcl |
0 |
pf2_vf_msix_tbl_size_hwtcl |
0 |
pf2_vf_msix_tbl_offset_hwtcl |
0 |
pf2_vf_msix_tbl_bir_hwtcl |
0 |
pf2_vf_msix_pba_offset_hwtcl |
0 |
pf2_vf_msix_pba_bir_hwtcl |
0 |
pf3_vf_msix_tbl_size_hwtcl |
0 |
pf3_vf_msix_tbl_offset_hwtcl |
0 |
pf3_vf_msix_tbl_bir_hwtcl |
0 |
pf3_vf_msix_pba_offset_hwtcl |
0 |
pf3_vf_msix_pba_bir_hwtcl |
0 |
rx_polinv_soft_logic_enable |
0 |
enable_soft_dfe |
0 |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |