subsys_pcie_clk_125
2017.10.31.03:29:03
Datasheet
Overview
Memory Map
clk_125
altera_clock_bridge v17.1
Parameters
DERIVED_CLOCK_RATE
125714286
EXPLICIT_CLOCK_RATE
125000000
NUM_CLOCK_OUTPUTS
1
deviceFamily
UNKNOWN
generateLegacySim
false
Software Assignments
(none)
generation took 0.00 seconds
rendering took 0.00 seconds